Programmable Interrupt Controller
11 Programmable Interrupt Controller
In IRQ edge trigger mode, when an external interrupt signal is asserted (according to the programmed
polarity), it must remain asserted for at least 3 system clocks (SYSCLK periods).
12 JTAG
This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the
MPC8572E.
Table 52
provides the JTAG AC timing specifications as defined in
Figure 37
through
Figure 39.
Table 52. JTAG AC Timing Specifications (Independent of SYSCLK)
1
DD
of 3.3 V ± 5%.
Parameter
JTAG external clock frequency of operation
JTAG external clock cycle time
JTAG external clock pulse width measured at 1.4 V
JTAG external clock rise and fall times
TRST assert time
Input setup times:
Boundary-scan data
TMS, TDI
Input hold times:
Boundary-scan data
TMS, TDI
Valid times:
Boundary-scan data
TDO
Output hold times:
Boundary-scan data
TDO
Symbol
2
f
JTG
t
JTG
t
JTKHKL
t
JTGR
& t
JTGF
t
TRST
t
JTDVKH
t
JTIVKH
t
JTDXKH
t
JTIXKH
t
JTKLDV
t
JTKLOV
t
JTKLDX
t
JTKLOX
Min
0
30
15
0
25
4
0
20
25
4
4
30
30
Max
33.3
—
—
2
—
—
—
Unit
MHz
ns
ns
ns
ns
ns
Notes
—
—
—
6
3
4
ns
—
—
ns
20
25
ns
—
—
5
5
4
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
65
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
