I
2
C
13.2
I
2
C AC Electrical Specifications
Table 54. I
2
C AC Electrical Specifications
Table 54
provides the AC timing parameters for the I
2
C interfaces.
DD
of 3.3 V ± 5%. All values refer to V
IH
(min) and V
IL
(max) levels (see
Table 2).
Parameter
SCL clock frequency
Low period of the SCL clock
High period of the SCL clock
Setup time for a repeated START condition
Hold time (repeated) START condition (after this period, the first
clock pulse is generated)
Data setup time
Data input hold time:
CBUS compatible masters
I
2
C bus devices
Data output delay time
Setup time for STOP condition
Bus free time between a STOP and START condition
Noise margin at the LOW level for each connected device
(including hysteresis)
Noise margin at the HIGH level for each connected device
(including hysteresis)
Capacitive load for each bus line
Symbol
1
f
I2C
t
I2CL
t
I2CH
t
I2SVKH
t
I2SXKL
t
I2DVKH
t
I2DXKL
Min
0
1.3
0.6
0.6
0.6
100
—
0
2
400
—
—
—
—
—
—
—
0.9
3
—
—
—
—
400
Unit
kHz
4
μs
μs
μs
μs
ns
μs
t
I2OVKL
t
I2PVKH
t
I2KHDX
V
NL
V
NH
Cb
—
0.6
1.3
0.1
×
OV
DD
0.2
×
OV
DD
—
μs
μs
μs
V
V
pF
Notes:
1.The symbols used for timing specifications herein follow the pattern t
(first two letters of functional block)(signal)(state)(reference)(state)
for
inputs and t
(first two letters of functional block)(reference)(state)(signal)(state)
for outputs. For example, t
I2DVKH
symbolizes I
2
C timing (I2)
with respect to the time data input signals (D) reach the valid state (V) relative to the t
I2C
clock reference (K) going to the high
(H) state or setup time. Also, t
I2SXKL
symbolizes I
2
C timing (I2) for the time that the data with respect to the START condition
(S) went invalid (X) relative to the t
I2C
clock reference (K) going to the low (L) state or hold time. Also, t
I2PVKH
symbolizes I
2
C
timing (I2) for the time that the data with respect to the STOP condition (P) reaching the valid state (V) relative to the t
I2C
clock
reference (K) going to the high (H) state or setup time.
2. As a transmitter, the MPC8572E provides a delay time of at least 300 ns for the SDA signal (referred to the VIHmin of the
SCL signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START or STOP
condition. When the MPC8572E acts as the I2C bus master while transmitting, the MPC8572E drives both SCL and SDA.
As long as the load on SCL and SDA are balanced, the MPC8572E would not cause unintended generation of START or
STOP condition. Therefore, the 300 ns SDA output delay time is not a concern. If, under some rare condition, the 300 ns SDA
output delay time is required for the MPC8572E as transmitter, applicat ion note AN2919 referred to in note 4 below is
recommended.
3.The maximum t
I2OVKL
has only to be met if the device does not stretch the LOW period (t
I2CL
) of the SCL signal.
4. The requirements for I
2
C frequency calculation must be followed. Refer to Freescale application note AN2919,
Determining
the I
2
C Frequency Divider Ratio for SCL.
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
68
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
