I
2
C
Figure 39
provides the boundary-scan timing diagram.
JTAG
External Clock
VM
t
JTDVKH
t
JTDXKH
Boundary
Data Inputs
t
JTKLDV
t
JTKLDX
Boundary
Data Outputs
t
JTKLDZ
Boundary
Data Outputs
Output Data Valid
VM = Midpoint Voltage (OVDD/2)
Output Data Valid
Input
Data Valid
VM
Figure 39. Boundary-Scan Timing Diagram
13 I
2
C
This section describes the DC and AC electrical characteristics for the I
2
C interfaces of the MPC8572E.
13.1
I
2
C DC Electrical Characteristics
Table 53. I
2
C DC Electrical Characteristics
Parameter
Symbol
V
IH
V
IL
V
OL
t
I2KHKL
I
I
C
I
Min
0.7
×
OV
DD
–0.3
0
0
–10
—
Max
OV
DD
+ 0.3
0.3
×
OV
DD
0.4
50
10
10
Unit
V
V
V
ns
μA
pF
Notes
—
—
1
2
3
—
Table 53
provides the DC electrical characteristics for the I
2
C interfaces.
Input high voltage level
Input low voltage level
Low level output voltage
Pulse width of spikes which must be suppressed by the
input filter
Input current each I/O pin (input voltage is between
0.1
×
OV
DD
and 0.9
×
OV
DD
(max)
Capacitance for each I/O pin
Notes:
1. Output voltage (open drain or open collector) condition = 3 mA sink current.
2. Refer to the
MPC8572E PowerQUICC™ III Integrated Host Processor Family Reference Manual
for information on the digital
filter used.
3. I/O pins will obstruct the SDA and SCL lines if OV
DD
is switched off.
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
67
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
