MB89374
s
BLOCK DIAGRAM
The DLC internal block diagram is shown below. The DLC consists of the SIU, BRG, DPLL, read/write control, and DMA interface sections.
IRQT
BRG1, BRG2 and DPLL sections
T
x
TCLK
BRG2
SCLK/DSR#
T
x
CTS#
Prescaler
DCD#
LOC#/RTS#
TURN
switching
BRG1
R
x
DPLL
R
x
R
x
FD#/DTR#
T
X
LAST#/CI#
MSR
MCR
SIU section
CRCC
DMA
interface sec-
tion
Odel
Decoder
T
X
DACK#/PI2
Receiver
controller
R
x
C
PortR
R
X
CO#/PO1
T
x
T
x
C
T
X
CO#/PO0
T
X
CI#/PI1
R
X
CI#/PI0
IRQ
T
X
IER
R
X
IER
REQR
MASKR
T
X
DRQ/PO2
Status
FIFO
ShiftR
Receive data
FIFO
R
X
DRQ/PO3
R
X
DACK#/PI3
SDR
R
X
CR
R
X
SR0, 1
Read/write
control
section
CRCG
Transmitter
controller
Command
FIFO
CLK
FORMAT#
RD#/DS#
WR#/R/W#
CS#
A4 to A0
D7 to D0
R
X
D
T
X
D
TURN
switching
ShiftR
Oins
coder
Transmit data
FIFO
V
CC
V
SS
RESET#
T
X
CR
T
X
SR
SDR
Indicates selected circuits
8
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