MB89374
s
PIN DESCRIPTION
Pin No.
DIP
QFP
Symbol
I/O
Level*
Description
Transmit clock-output or port-output 1 pin:
This pin is selected as the clock-output pin or port-output pin
by the TxC0 and TxC1 bits of the transfer mode register
(SMR2) and by the TxBRGEN bit of the transmit mode
register (SMR3).
Transmit clock-input or port-input 1 pin:
This pin is selected as the clock-input pin or port-input pin by
the TxC0 and TxC1 bits of the transfer mode register
(SMR2) and by the TxBRGEN bit of the transmit mode
register (SMR3).
Receive clock-output or port-output 0 pin:
This pin is selected as the clock-output pin or port-output pin
by the RxC0 and RxC1 bits of the transfer mode register
(SMR2).
Receive clock-input or port-input 0 pin:
This pin is selected as the clock-input pin or port-input pin by
the RxC0 and RxC1 bits of the transfer mode register
(SMR2).
Loop on-line control or request-to-send pin:
This pin serves as the LOC# output pin in the LOOP mode
and as the RTS# output pin in the BOP mode. If it is used as
the LOC# output pin, it functions as an on-line/off-line control
pin. If it is used as the RTS# output pin, it outputs a LOW
level when the RTS bit of the modem control register (MCR)
is set to 1, and outputs a HIGH level when the RTS bit is set
to 0.
Flag-detect or data-terminal-ready pin:
This pin is selected as the flag-detect or data-terminal-ready
pin by the FD or DTR bits of the transmit mode register
(SMR3). If it is used as the FD# pin, it outputs a LOW level
during one cycle of the receive clock after receiving the last
bit of the flag. If it is used as the DTR# pin, it outputs a LOW
level when the DTR bit of the modem control register (MCR)
is set to 1, and a HIGH level when the DTR bit is set to 0.
Data-carrier-detect pin:
The DCD bit of the modem status register (MSR) displays 1
when the pin input level is LOW and 0 when the input level is
HIGH.
Clear-to-send pin:
The CTS bit of the modem status register (MSR) displays 1
when the pin input level is LOW, and displays 0 when the
input level is HIGH. The DLC is placed in the transmission-
enable state when this pin is set to the CTSAUTO mode, and
by the TxE bit of the transmission control register (TxCR).
Transmission is enabled/disabled according to the input level
of the CTS# pin; transmission is enabled when the pin input
level is LOW and disabled when the input level is HIGH.
30
5
T
X
CO#/PO1
O
L
31
6
T
X
CI#/PI1
I
—
26
48
R
X
CO#/PO0
O
L
27
2
R
X
CI#/PI0
I
—
22
44
LOC#/RTS#
O
H
34
9
FD#/DTR#
O
H
25
47
DCD#
I
—
24
46
CTS#
I
—
Signals suffixed by the symbol # are negative logic.
* : Pin output level when reset
4
(Continued)
FUJITSU [ FUJITSU COMPONENT LIMITED. ]
