GS1559 Data Sheet
4.10.6 Error Correction and Insertion
In addition to signal error detection and indication, the GS1559 may also correct
certain types of errors by inserting corrected code words, checksums and CRC
values into the data stream. These features are only available in SMPTE mode and
IOPROC_EN/
DIS
must be set HIGH. Individual correction features may be enabled
or disabled via the IOPROC_DISABLE register (Table
All of the IOPROC_DISABLE register bits default to '0' after device reset, enabling
all of the processing features. To disable any individual error correction feature, the
host interface must set the corresponding bit HIGH in the IOPROC_DISABLE
register.
Table 4-14: Host Interface Description for Internal Processing Disable Register
Register Name
IOPROC_DISABLE
Address: 000h
Bit
15-9
8
Name
–
H_CONFIG
Description
Not Used.
Horizontal sync timing output configuration. Set
LOW for active line blanking timing. Set HIGH for H
blanking based on the H bit setting of the TRS
words. See
Not Used.
Illegal Code re-mapping. Correction of illegal code
words within the active picture. Set HIGH to disable.
The IOPROC_EN/DIS pin must be set HIGH.
Error Detection & Handling (EDH) Cyclical
Redundancy Check (CRC) error correction
insertion. In SD mode set HIGH to disable. The
IOPROC_EN/DIS pin must be set HIGH.
Ancillary Data Check-sum insertion. Set HIGH to
disable. The IOPROC_EN/DIS pin must be set
HIGH.
Y and C line based CRC insertion. In HD mode,
inserts line based CRC words in both the Y and C
channels. Set HIGH to disable. The
IOPROC_EN/DIS pin must be set HIGH.
Y and C line number insertion. In HD mode set
HIGH to disable. The IOPROC_EN/DIS pin must be
set HIGH.
Timing Reference Signal Insertion. Set HIGH to
disable. The IOPROC_EN/DIS pin must be set
HIGH.
R/W
–
Default
–
0
7-6
5
–
ILLEGAL_REMAP
–
R/W
–
0
4
EDH_CRC_INS
R/W
0
3
ANC_CSUM_INS
R/W
0
2
CRC_INS
R/W
0
1
LNUM_INS
R/W
0
0
TRS_INS
R/W
0
30572 - 4
July 2005
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GENNUM [ GENNUM CORPORATION ]
