GS1559 Data Sheet
As described in
the data bus outputs will be
forced to logic LOW if the device is set to operate in master mode but cannot
identify SMPTE TRS ID or DVB-ASI sync words in the input data stream.
4.11.5 Parallel Output Clock (PCLK)
The frequency of the PCLK output signal of the GS1559 is determined by the
output data format.
below lists the possible output signal formats and
their corresponding parallel clock rates. Note that DVB-ASI output will always be in
10-bit format, regardless of the setting of the 20bit/10bit pin.
Table 4-16: Parallel Data Output Format
Status / Control Signals*
Output Data Format
DOUT
[19:10]
DOUT
[9:0]
PCLK
20bit/
10bit
SD/HD
SMPTE_BYPASS
DVB_ASI
SMPTE MODE
20bit DEMULTIPLEXED SD
10bit MULTIPLEXED SD
20bit DEMULTIPLEXED HD
LUMA
LUMA /
CHROMA
LUMA
CHROMA
FORCED
LOW
CHROMA
13.5MHz
27MHz
74.25 or
74.25/
1.001MHz
148.5 or
148.5/
1.001MHz
HIGH
LOW
HIGH
HIGH
HIGH
LOW
HIGH
HIGH
HIGH
LOW
LOW
LOW
10bit MULTIPLEXED HD
LUMA /
CHROMA
FORCED
LOW
LOW
LOW
HIGH
LOW
DVB-ASI MODE
10bit DVB-ASI
DVB-ASI
DATA
DVB-ASI
DATA
FORCED
LOW
FORCED
LOW
27MHz
27MHz
HIGH
LOW
HIGH
HIGH
LOW
LOW
HIGH
HIGH
DATA-THROUGH MODE**
20bit DEMULTIPLEXED SD
10bit MULTIPLEXED SD
20bit DEMULTIPLEXED HD
DATA
DATA
DATA
DATA
FORCED
LOW
DATA
13.5MHz
27MHz
74.25 or
74.25/
1.001MHz
148.5 or
148.5/
1.001MHz
HIGH
LOW
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
LOW
LOW
LOW
10bit MULTIPLEXED HD
DATA
FORCED
LOW
LOW
LOW
LOW
LOW
*NOTE1: Recall that SD/HD, SMPTE_BYPASS, and DVB_ASI are input control pins in slave mode to be set by the application layer, but are
output status signals set by the device in master mode.
**NOTE 2: Data-Through mode is only available in slave mode
30572 - 4
July 2005
63 of 74
GENNUM [ GENNUM CORPORATION ]
