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IDT72211L15J PDF Datasheet浏览和下载

型号:
IDT72211L15J
PDF下载:
下载PDF文件 在线浏览文档
内容描述:
CMOS SyncFIFOO 64 ×9 , 256 ×9 , 512× 9 , 1024 X 9 , 2048 ×9和4096 ×9 [CMOS SyncFIFOO 64 X 9, 256 x 9, 512 x 9, 1024 X 9, 2048 X 9 and 4096 x 9]
文件大小:
155 K
文件页数:
14 Pages
品牌Logo:
品牌名称:
IDT [ INTEGRATED DEVICE TECHNOLOGY ]



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IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN CONFIGURATION
RS
D
2
D
3
D
5
D
6
D
4
D
2
D
3
D
4
D
5
D
6
D
7
INDEX
D
8
32 31 30 29 28 27 26 25
4
D
1
5
6
7
8
9
10
11
12
13
24
23
22
21
20
19
18
17
WEN1
WCLK
WEN2/LD
V
CC
Q
8
Q
7
Q
6
Q
5
3
2
1
32 31 30
29
28
27
26
25
24
23
22
21
RS
WEN1
WCLK
WEN2/LD
V
CC
Q
8
Q
7
Q
6
Q
5
D
1
D
0
PAF
PAE
GND
REN1
RCLK
REN2
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
D
0
PAF
PAE
GND
REN1
RCLK
REN2
OE
14 15 16 17 18 19 20
Q
1
Q
2
EF
Q
3
Q
4
2655 drw 02
OE
EF
FF
Q
0
Q
1
Q
3
Q
2
Q
4
FF
Q
0
D
7
D
8
INDEX
2655 drw02a
TQFP (PR32-1, order code: PF)
TOP VIEW
PLCC (J32-1, order code: J)
TOP VIEW
PIN DESCRIPTIONS
Symbol
Name
D
0
-D
8
Data Inputs
RS
Reset
WCLK
WEN1
Write Clock
Write Enable 1
WEN2/
LD
Write Enable 2/
Load
Q
0
-Q
8
RCLK
REN1
REN2
OE
EF
PAE
PAF
FF
Data Outputs
Read Clock
Read Enable 1
Read Enable 2
Output Enable
Empty Flag
Programmable
Almost-Empty Flag
Programmable
Almost-Full Flag
Full Flag
Power
Ground
V
CC
GND
I/O
Description
I Data inputs for a 9-bit bus.
I When
RS
is set LOW, internal read and write pointers are set to the first location of the RAM array,
FF
and
PAF
go HIGH, and
PAE
and
EF
go LOW. A reset is required before an initial WRITE after power-up.
I Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when the Write Enable(s) are asserted.
I If the FIFO is configured to have programmable flags,
WEN1
is the only write enable pin. When
WEN1
is LOW,
data is written into the FIFO on every LOW-to-HIGH transition WCLK. If the FIFO is configured to have two write
enables,
WEN1
must be LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into
the FIFO if the
FF
is LOW.
I The FIFO is configured at reset to have either two write enables or programmable flags. If WEN2/
LD
is
HIGH
at reset, this pin operates as a second write enable. If WEN2/
LD
is LOW at reset, this pin operates as a control
to load and read the programmable flag offsets. If the FIFO is configured to have two write enables,
WEN1
must
be LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO if the
FF
is
LOW. If the FIFO is configured to have programmable flags, WEN2/
LD
is held LOW to write or read the
programmable flag offsets.
O Data outputs for a 9-bit bus.
I Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when
REN1
and
REN2
are asserted.
I When
REN1
and
REN2
are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK.
Data will not be read from the FIFO if the
EF
is LOW.
I When
REN1
and
REN2
are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK.
Data will not be read from the FIFO if the
EF
is LOW.
I When
OE
is LOW, the data output bus is active. If
OE
is HIGH, the output data bus will be in a high-impedance
state.
O When
EF
is LOW, the FIFO is empty and further data reads from the output are inhibited. When
EF
is HIGH, the
FIFO is not empty.
EF
is synchronized to RCLK.
O When
PAE
is LOW, the FIFO is almost-empty based on the offset programmed into the FIFO. The default
offset at reset is Empty+7.
PAE
is synchronized to RCLK.
O When
PAF
is LOW, the FIFO is almost-full based on the offset programmed into the FIFO. The default offset
at reset is Full-7.
PAF
is synchronized to WCLK.
O When
FF
is LOW, the FIFO is full and further data writes into the input are inhibited. When
FF
is HIGH, the FIFO
is not full.
FF
is synchronized to WCLK.
One +5 volt power supply pin.
One 0 volt ground pin.
2