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STA308 参数 Datasheet PDF下载

STA308图片预览
型号: STA308
PDF下载: 下载PDF文件 查看货源
内容描述: 使用DDX ™多声道数字音频处理器 [MULTICHANNEL DIGITAL AUDIO PROCESSOR WITH DDX⑩]
分类和应用:
文件页数/大小: 33 页 / 259 K
品牌: STMICROELECTRONICS [ STMICROELECTRONICS ]
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STA308
3.0.3 Bass Management Enable
BIT
5
R/W
R/W
RST
0
NAME
BME
DESCRIPTION
Bass Management Enable : 0 – No Bass Management
1 – Bass Management operation on channel 6, scale and add inputs
Channel 6 of the STA308 features a bass management mode that enables redirection of information in all other
channels to this channel and which can then be filtered appropriately using the EQ(Biquad) section. Setting the
BME bit selects the output of the scale and mix block for channel 6 instead of the output of the channel mapping
block. The settings for the scale and mix block are provided by the CxBMS registers
3.0.4 DDX Headphone Output Enable
BIT
6
R/W
R/W
RST
0
NAME
HPE
DESCRIPTION
DDX Headphone Enable :
0 – Channels 7,8 normal DDX operation.
1 – Channels 7,8 DDX Headphone operation.
Channels 7 and 8 of the STA308 have the option to be processed for headphones. The headphone output can
then be driven using an appropriate output device. This signal is a fully differential 3-wire drive called DDX
Headphone
3.0.5 Max Power Correction
BIT
7
R/W
R/W
RST
1
NAME
MPC
DESCRIPTION
Max Power Correction : Setting of 1 enables DDX correction for THD reduction
near maximum power output.
Setting the MPC bit turns on special processing that corrects the DDX power device at high power. This mode
should lower the THD+N of a full DDX system at maximum power output and slightly below. This mode will only
be operational in OM= 00 or 10.
3.1 Configuration Register B (address 01h)
BIT
NAME
RST
D7
DRC
0
D6
ZCE
1
D5
SAIFB
0
D4
SAI2
0
D3
SAI1
0
D2
SAI0
0
D1
ZDE
1
D0
DSPB
0
3.1.1 DSP Bypass
BIT
0
R/W
R/W
RST
0
NAME
DSPB
DESCRIPTION
DSP Bypass Bit : 0 – Normal Operation
1 – Bypass of Biquad and Bass/Treble Functionality
Setting the DSPB bit bypasses the biquad and bass/treble functionality of the STA308.
3.1.2 Zero-Detect Mute Enable
BIT
1
R/W
R/W
RST
1
NAME
ZDE
DESCRIPTION
Zero-Detect Mute Enable : Setting of 1 enables the
automatic zero-detect mute
Setting the ZDE bit enables the zero-detect automatic mute.
The zero-detect circuit looks at the input data to each processing channel after the channel mapping block. If
any channel receives 2048 consecutive zero value samples (regardless of fs) then that individual channel is
muted if this function is enabled.
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