STA308
3.2.2 DDX Compensating Pulse Size Register
BIT
2
R/W
R/W
R/W
R/W
R/W
R/W
RST
NAME
CSZ0
CSZ1
CSZ2
CSZ3
CSZ4
DESCRIPTION
1
1
1
1
1
Contra Size Register : When OM(1,0) = 11, this register determines the
size of the DDX compensating pulse from 0 clock ticks to 31 clock periods.
3
4
5
6
CSZ(4..0)
00000
00001
…
Compensating Pulse Size
0 Clock period Compensating Pulse Size
1 Clock period Compensating Pulse Size
…
11111
31 Clock period Compensating Pulse Size
3.2.3 High-Pass Filter Bypass
BIT
R/W
RST
NAME
DESCRIPTION
7
R/W
0
HPB
High-Pass Filter Bypass Bit. Setting of one bypasses internal AC
coupling digital high-pass filter
The STA308 features an internal digital high-pass filter for the purpose of AC coupling. The purpose of this filter
is to prevent DC signals from passing through a DDX amplifier. DC signals can cause speaker damage
3.3 Configuration Register D (address 03h)
BIT
NAME
RST
D7
BQL
0
D6
PSL
0
D5
COS1
1
D4
COS0
0
D3
C78BO
0
D2
C56BO
0
D1
C34BO
0
D0
C12BO
0
3.3.1 Binary Output Enable Registers
BIT
0
R/W
R/W
R/W
R/W
R/W
RST
NAME
C12BO
C34BO
C56BO
C78BO
DESCRIPTION
0
0
0
0
Channels 1&2, 3&4, 5&6, 7&8 Binary Output Mode Enable
Bits. A setting of 0 indicates ordinary DDX tri-state output. A
setting of 1 indicates binary output mode.
1
2
3
Each two-channel pair of outputs can be set to output a binary PWM stream. In this mode, output A
of a channel will be considered the positive output and output B is negative inverse. For example, setting C34BO
= 1 sets channels 3&4 to Binary Output (PWM) Mode.
3.3.2 Clock Output Select
BIT
4
R/W
R/W
R/W
RST
NAME
COS0
COS1
DESCRIPTION
Clock Output Select
Clock Output Select
0
1
5
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STMICROELECTRONICS [ ST ]
