STA308
3.1.3 Serial Audio Input Interface First Bit
BIT
R/W
RST
NAME
DESCRIPTION
5
R/W
0
SAIFB
Determines MSB or LSB first for all SAI formats
0 – MSB First, 1 – LSB First
3.1.4 Zero-Crossing Volume Enable
BIT
R/W
RST
NAME
DESCRIPTION
Zero-Crossing Volume Enable :
6
R/W
1
ZCE
1 – Volume adjustments will only occur at digital zero-crossings
0 – Volume adjustments will occur immediately
The ZCE bit enables zero-crossing volume adjustments. When volume is adjusted on digital zero-crossings,
"zipper noise" is eliminated
3.1.5 Dynamic Range Compression/Anti-Clipping Bit
BIT
R/W
RST
NAME
DESCRIPTION
6
R/W
0
DRC
Dynamic Range Compression/Anti-Clipping
0 – Limiters act in Anti-Clipping Mode
1- Limiters act in Dynamic Range Compression Mode
Both limiters can be used in one of two ways, anti-clipping or dynamic range compression. When used in anti-
clipping mode the limiter threshold values are constant and dependent on the gain/attenuation settings applied
to the input signal. In dynamic range compression mode the limiter threshold values vary with the volume set-
tings allowing for limiting to occur independently of the gain/attenuation but dependent on the input signal
3.2 Configuration Register C (address 02h)
BIT
NAME
RST
D7
HPB
0
D6
CSZ4
1
D5
CSZ3
1
D4
CSZ2
1
D3
CSZ1
1
D2
CSZ0
1
D1
OM1
0
D0
OM0
0
3.2.1 DDX Power Output Mode
BIT
0
R/W
R/W
R/W
RST
NAME
OM0
DESCRIPTION
DDX Power Output Mode : Selects configuration of DDX output.
0
0
1
OM1
The DDX Power Output Mode selects how the DDX output timing is configured. Different power devices use
different output modes. The DDX recommended use is OM = 00. The variable mode uses the OMVx bits for
adjustment
OM(1,0)
00
Output Stage - Mode
Fixed Compensation for DDX-2060, DDX-2100 power amplifiers
Tapered Compensation for Discrete Output Stage
Full Power Mode
01
10
11
Variable Compensation (CSZx bits, see 3.3.2)
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STMICROELECTRONICS [ ST ]
