SNAS605 AP – MARCH 2013 – REVISED JUNE 2013
PLL1
External VCXO
or Tunable
Crystal
External
Loop Filter
PLL2
Up to 1 OSCout
OSCout
OSCout*
External
Loop Filter
CPout1
CLKinX
CLKinX*
Up to 3
inputs
R
Phase
Detector
PLL1
OSCin
CPout2
R
Input
Buffer
Phase
Detector
PLL2
Partially
Integrated
Loop Filter
Dual
Internal
VCOs
Divider
Digital Delay
Analog Delay
SDCLKoutY
SDCLKoutY*
7 SYSREF
or Device
Clocks
DCLKoutX
DCLKoutX*
7 Device
Clocks
N
N
7 blocks
SYSREF
Analog Delay
Digital Delay
Internal or external loopback, user programmable
LMK0482xB
1 Global SYSREF Divider
Figure 1-3. Simplified Functional Block Diagram for Nested 0-delay Dual Loop Mode
illustrates nested 0-delay mode. This is the same as cascaded except the clock out feedback is
to PLL1. The CLKin and CLKout have the same deterministic phase relationship but the VCXO's phase
will not be deterministic to the CLKin or CLKouts.
Table 1-3. Nested 0-delay Dual Loop Mode Register Configuration
Field
PLL1_NCLK_MUX
PLL2_NCLK_MUX
FB_MUX_EN
FB_MUX
OSCin_PD
CLKin0_OUT_MUX
CLKin1_OUT_MUX
VCO_MUX
Register
Address
0x13F
0x13F
0x13F
0x13F
0x140
0x147
0x147
0x138
Function
Selects the input to the PLL1 N divider.
Selects the input to the PLL2 N divider
Enables the Feedback Mux.
Selects the output of the Feedback Mux.
Powers down the OSCin port.
Selects where the output of CLKin0 is directed.
Selects where the output of CLKin1 is directed.
Selects the VCO 0, 1 or an external VCO
Value
1
0
1
0, 1, or 2
0
2
0 or 2
0 or 1
Selected Value
Feedback Mux
PLL2 P
Enabled
Select between DCLKout6,
DCLKout8, SYSREF
Powered up
PLL1
Fin or PLL1
VCO 0 or VCO 1
Copyright © 2013, Texas Instruments Incorporated
INTRODUCTION
Product Folder Links :LMK04826B,
5
TI [ TEXAS INSTRUMENTS ]
