MSP430G2x52
MSP430G2x12
SLAS722B
–
DECEMBER 2010
–
REVISED MARCH 2011
Table 2. Terminal Functions
TERMINAL
NO.
NAME
P1.0/
TA0CLK/
ACLK/
A0/
CA0
P1.1/
TA0.0/
A1/
CA1
P1.2/
TA0.1/
A2/
CA2
P1.3/
ADC10CLK/
CAOUT/
A3/
VREF-/VEREF/
CA3
P1.4/
SMCLK/
TA0.2/
A4/
VREF+/VEREF+/
CA4/
TCK
P1.5/
TA0.0/
SCLK/
A5/
CA5/
TMS
P1.6/
TA0.1/
SDO/
SCL/
A6/
CA6/
TDI/TCLK
8
7
14
I/O
7
6
7
I/O
6
5
6
I/O
5
4
5
I/O
4
3
4
I/O
3
2
3
I/O
2
1
2
I/O
14
PW
16
RSA
20
N, PW
General-purpose digital I/O pin
Timer0_A, clock signal TACLK input
ACLK signal output
ADC10 analog input A0
(1)
Comparator_A+, CA0 input
General-purpose digital I/O pin
Timer0_A, capture: CCI0A input, compare: Out0 output
ADC10 analog input A1
(1)
Comparator_A+, CA1 input
General-purpose digital I/O pin
Timer0_A, capture: CCI1A input, compare: Out1 output
ADC10 analog input A2
(1)
Comparator_A+, CA2 input
General-purpose digital I/O pin
ADC10, conversion clock output
(1)
Comparator_A+, output
ADC10 analog input A3
(1)
ADC10 negative reference voltage
(1)
Comparator_A+, CA3 input
General-purpose digital I/O pin
SMCLK signal output
Timer0_A, capture: CCI2A input, compare: Out2 output
ADC10 analog input A4
(1)
ADC10 positive reference voltage
(1)
Comparator_A+, CA4 input
JTAG test clock, input terminal for device programming and test
General-purpose digital I/O pin
Timer0_A, compare: Out0 output
USI: clk input in I2C mode; clk in/output in SPI mode
ADC10 analog input A5
(1)
Comparator_A+, CA5 input
JTAG test mode select, input terminal for device programming and test
General-purpose digital I/O pin
Timer0_A, compare: Out1 output
USI: Data output in SPI mode
USI: I2C clock in I2C mode
ADC10 analog input A6
(1)
Comparator_A+, CA6 input
JTAG test data input or test clock input during programming and test
I/O
DESCRIPTION
(1)
Available only on MSP430G2x52 devices.
5
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