SLES263 – NOVEMBER 2010
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DEVICE INFORMATION
Terminal Assignment
Both package types contains a heat slug that is located on the top side of the device for convenient thermal
coupling to the heat sink.
PHD PACKAGE
(TOP VIEW)
VDD
PSU_REF
NC
NC
NC
NC
GND
GND
GVDD_B
GVDD_A
BST_A
OUT_A
OUT_A
PVDD_A
PVDD_A
GND_A
DKD PACKAGE
(TOP VIEW)
Electrical Pin 1
Pin 1 Marker
White Dot
2
Product Folder Link(s):
OTW2
CLIP
READY
M1
M2
M3
GND
GND
GVDD_C
GVDD_D
BST_D
OUT_D
OUT_D
PVDD_D
PVDD_D
GND_D
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
OC_ADJ
RESET
C_STARTUP
INPUT_A
INPUT_B
VI_CM
GND
AGND
VREG
INPUT_C
INPUT_D
TEST
NC
NC
SD
OTW1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64-pins QFP package
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
GND_A
GND_B
GND_B
OUT_B
OUT_B
PVDD_B
PVDD_B
BST_B
BST_C
PVDD_C
PVDD_C
OUT_C
OUT_C
GND_C
GND_C
_
GND_D
PSU_REF
VDD
OC_ADJ
RESET
C_STARTUP
INPUT_A
INPUT_B
VI_CM
GND
AGND
VREG
INPUT_C
INPUT_D
TEST
NC
NC
SD
OTW
READY
M1
M2
M3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
GVDD_AB
BST_A
PVDD_A
PVDD_A
OUT_A
OUT_A
GND_A
GND_B
OUT_B
PVDD_B
BST_B
BST_C
PVDD_C
OUT_C
GND_C
GND_D
OUT_D
OUT_D
PVDD_D
PVDD_D
BST_D
GVDD_CD
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
44 pins PACKAGE
(TOP VIEW)
PIN ONE LOCATION PHD PACKAGE
Copyright © 2010, Texas Instruments Incorporated
TI [ TEXAS INSTRUMENTS ]
