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SLES263 – NOVEMBER 2010
MODE SELECTION PINS
MODE PINS
M3
0
0
0
0
1
1
1
1
(1)
(2)
M2
0
0
1
1
0
0
1
1
M1
0
1
0
1
0
1
0
1
PWM INPUT
(1)
2N
—
2N
1N
1N
2N
1N
OUTPUT
CONFIGURATION
2 × BTL
—
2 × BTL
1 × BTL +2 × SE
4 × SE
1 × PBTL
AD mode
Reserved
BD mode
AD mode
AD mode
INPUT_C
(2)
0
1
Reserved
INPUT_D
(2)
0
0
AD mode
BD mode
DESCRIPTION
The 1N and 2N naming convention is used to indicate the number of PWM lines to the power stage per channel in a specific mode.
INPUT_C and INPUT_D are used to select between a subset of AD and BD mode operations in PBTL mode.
PACKAGE HEAT DISSIPATION RATINGS
(1)
PARAMETER
R
qJC
(°C/W) – 2 BTL or 4 SE channels
R
qJC
(°C/W) – 1 BTL or 2 SE channel(s)
R
qJC
(°C/W) – 1 SE channel
Pad area
(1)
(2)
(2)
TAS5631BPHD
2.63
4.13
6.45
64 mm
2
TAS5631BDKD
1.4
2.04
3.45
80 mm
2
R
qJC
is junction-to-case; R
qCH
is case-to-heatsink.
R
qCH
is an important consideration. Assume a 2-mil (0.051-mm) thickness of thermal grease with a thermal conductivity of 2.5 W/mK
between the pad area and the heat sink and both channels active. The R
qCH
with this condition is 1.1°C/W for the PHD package and
0.44°C/W for the DKD package.
Table 1. ORDERING INFORMATION
(1)
T
A
0°C–70°C
0°C–70°C
(1)
PACKAGE
TAS5631BPHD
TAS5631BDKD
DESCRIPTION
64-pin HTQFP
44-pin PSOP3
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at
Copyright © 2010, Texas Instruments Incorporated
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