TC55V8512J/FT-12,-15
BLOCK DIAGRAM
A0
A1
A4
A8
A9
A12
A14
A15
A16
A17
ROW ADDRESS
BUFFER
V
DD
GND
ROW
DECODER
MEMORY CELL ARRAY
512
×
1,024
×
8
(4,194,304)
CE
I/O1
I/O2
I/O3
I/O4
I/O5
I/O5
I/O7
I/O8
DATA OUTPUT
BUFFER
CE
COLUMN ADDRESS BUFFER
CLOCK
GENERATOR
A2 A3 A5 A6 A7 A10 A11A13 A18
VALUE
−0.5
to 4.6
−0.5*
to 4.6
−0.5*
to V
DD
+
0.5**
1.4
260
−65
to 150
−10
to 85
DATA INPUT
BUFFER
SENSE AMP
COLUMN DECODER
WE
OE
CE
CE
MAXIMUM RATINGS
SYMBOL
V
DD
V
IN
V
I/O
P
D
T
solder
T
stg
T
opr
Power Supply Voltage
Input Terminal Voltage
Input/Output Terminal Voltage
Power Dissipation
Soldering Temperature (10s)
Storage Temperature
Operating Temperature
RATING
UNIT
V
V
V
W
°C
°C
°C
*:
−1.5
V with a pulse width of 20%�½�t
RC
min (4 ns max)
**:
V
DD
+
1.5 V with a pulse width of 20%�½�t
RC
min (4 ns max)
DC RECOMMENDED OPERATING CONDITIONS
(Ta
=
0° to 70°C)
SYMBOL
V
DD
V
IH
V
IL
PARAMETER
Power Supply Voltage
Input High Voltage
Input Low Voltage
MIN
3.0
2.0
−0.3*
TYP
3.3
MAX
3.6
V
DD
+
0.3**
0.8
UNIT
V
V
V
*:
−1.0
V with a pulse width of 20%�½�t
RC
min (4 ns max)
**:
V
DD
+
1.0 V with a pulse width of 20%�½�t
RC
min (4 ns max)
2001-12-19
2/10
TOSHIBA [ TOSHIBA SEMICONDUCTOR ]
