WM2604
Production Data
SERIAL INTERFACE
t
WL
SCLK
1
t
SUD
DIN
D15
t
SUCSFS
NCS
t
WHFS
FS
t
SUFSCLK
t
SUC16FS
t
HD
D14
D13
D12
D1
D0
2
t
WH
3
4
5 15
16
t
SUC16CS
Figure 1 Timing Diagram
Test Conditions:
R
L
= 10kΩ, C
L
= 100pF. AVDD = DVDD = 5V
±
10%, V
REF
= 2.048V and AVDD = DVDD = 3V
±
10%, V
REF
= 1.024V over
recommended operating free-air temperature range (unless noted otherwise)
SYMBOL
t
SUCSFS
t
SUFSCLK
t
SUC16FS
TEST CONDITIONS
Setup time NCS low before negative FS edge.
Setup time FS low before first negative SCLK edge.
Setup time, sixteenth negative SCLK edge after FS low
on which D0 is sampled before rising edge of FS.
Setup time, sixteenth positive SCLK edge (first positive
after D0 sampled) before NCS rising edge.
If FS is used instead of the sixteenth positive edge to
update the DAC, then the setup time is between the FS
rising edge and the NCS rising edge.
Pulse duration, SCLK high.
Pulse duration, SCLK low.
Setup time, data ready before SCLK falling edge.
Hold time, data held valid after SCLK falling edge.
Pulse duration, FS high.
MIN
10
8
10
10
TYP
MAX
UNIT
ns
ns
ns
ns
t
SUC16CS
t
WHCLK
t
WLCLK
t
SUDCLK
t
HDCLK
t
WHFS
25
25
8
5
20
ns
ns
ns
ns
ns
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 June 1999
6
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
