CoolRunner-II CPLD Family
nally generated DataGATE control logic can be assigned to
this I/O pin with the BUFG=DATA_GATE attribute.
DataGATE Assertion Rail
MC1
MC2
MC1
MC2
Latch
R
To AIM
PLA
Latch
PLA
Latch
To AIM
MC16
MC1
MC2
MC16
MC1
MC2
To AIM
AIM
PLA
PLA
Latch
Latch
To AIM
MC16
MC16
To AIM
DS090_06_111201
Figure 6:
DataGATE Architecture (output drivers not shown)
Global Signals
Global signals, clocks (GCK), sets/resets (GSR), and output
enables (GTS), are designed to strongly resemble each
other. This approach enables design software to make the
best utilization of their capabilities. Each global capability is
supplemented by a corresponding product term version.
shows the common structure of the global signal
trees. The pin input is buffered, then drives multiple internal
global signal traces to deliver low skew and reduce loading
delays. GCK, GSR, and GTS can also be used as general
purpose I/Os if they are not needed as global signals. The
DataGATE assertion rail is also a global signal.
DS090_07_101001
Figure 7:
Global Clocks (GCK), Sets/Resets (GSR), and
Output Enables (GTS)
8
DS090 (v3.1) September 11, 2008
Product Specification
XILINX [ XILINX, INC ]
