CoolRunner-II CPLD Family
path. The BSC and ISP block has the JTAG controller and
In-System Programming Circuits.
BSC Path
Clock and Control Signals
R
Function
Block 1
I/O Pin
I/O Pin
Function
Block n
MC1
MC2
16 FB
16 FB
I/O Pin
I/O Pin
MC1
MC2
I/O Blocks
16
PLA
40
AIM
PLA
40
16
I/O Pin
16
MC16
Direct Inputs
MC16
Direct Inputs
16
I/O Blocks
I/O Pin
JTAG
BSC and ISP
DS090_01_121201
Figure 1:
CoolRunner-II CPLD Architecture
Function Block
The CoolRunner-II CPLD FBs contain 16 macrocells, with
40 entry sites for signals to arrive for logic creation and con-
nection. The internal logic engine is a 56 product term PLA.
All FBs, regardless of the number contained in the device,
are identical. For a high-level view of the FB, see
MC1
MC2
flexible, and very robust when compared to fixed or cas-
caded product term FBs.
Classic CPLDs typically have a few product terms available
for a high-speed path to a given macrocell. They rely on
capturing unused p-terms from neighboring macrocells to
expand their product term tally, when needed. The result of
this architecture is a variable timing model and the possibil-
ity of stranding unusable logic within the FB.
The PLA is different — and better. First, any product term
can be attached to any OR gate inside the FB macrocell(s).
Second, any logic function can have as many p-terms as
needed attached to it within the FB, to an upper limit of 56.
Third, product terms can be re-used at multiple macrocell
OR functions so that within a FB, a particular logical product
need only be created once, but can be re-used up to 16
times within the FB. Naturally, this plays well with the fitting
software, which identifies product terms that can be shared.
The software places as many of those functions as it can
into FBs, so it happens for free. There is no need to force
macrocell functions to be adjacent or any other restriction
save residing in the same FB, which is handled by the soft-
ware. Functions need not share a common clock, common
set/reset, or common output enable to take full advantage of
the PLA. Also, every product term arrives with the same
time delay incurred. There are no cascade time adders for
putting more product terms in the FB. When the FB product
term budget is reached, there is a small interconnect timing
penalty to route signals to another FB to continue creating
logic. Xilinx design software handles all this automatically.
DS090 (v3.1) September 11, 2008
Product Specification
40
PLA
16
Out
To AIM
MC16
3
Global
Set/Reset
Global
Clocks
DS090_02_101001
Figure 2:
CoolRunner-II CPLD Function Block
At the high level, the product terms (p-terms) reside in a
programmable logic array (PLA). This structure is extremely
4
XILINX [ XILINX, INC ]
