R
Spartan-3 FPGA Family: Introduction and Ordering Information
The recommended memory for storing the configuration
data is the low-cost Xilinx Platform Flash PROM family,
which includes the XCF00S PROMs for serial configuration
and the higher density XCF00P PROMs for parallel or serial
configuration.
Configuration
Spartan-3 FPGAs are programmed by loading configuration
data into robust, reprogrammable, static CMOS configura-
tion latches (CCLs) that collectively control all functional
elements and routing resources. Before powering on the
FPGA, configuration data is stored externally in a PROM or
some other nonvolatile medium either on or off the board.
After applying power, the configuration data is written to the
FPGA using any of five different modes: Master Parallel,
Slave Parallel, Master Serial, Slave Serial, and Boundary
Scan (JTAG). The Master and Slave Parallel modes use an
8-bit wide SelectMAP port.
Standard
Category
Single-Ended
GTL
Gunning Transceiver Logic
I/O Capabilities
The SelectIO feature of Spartan-3 devices supports 18 sin-
gle-ended standards and 8 differential standards as listed in
Many standards support the DCI feature, which
uses integrated terminations to eliminate unwanted signal
reflections..
V
CCO
(V)
N/A
Table 2:
Signal Standards Supported by the Spartan-3 Family
Description
Class
Terminated
Plus
HSTL
High-Speed Transceiver Logic
1.5
I
III
1.8
I
II
III
LVCMOS
Low-Voltage CMOS
1.2
1.5
1.8
2.5
3.3
LVTTL
PCI
SSTL
Low-Voltage Transistor-Transistor Logic
Peripheral Component Interconnect
Stub Series Terminated Logic
3.3
3.0
1.8
N/A
N/A
N/A
N/A
N/A
N/A
33 MHz
(1)
N/A (±6.7 mA)
N/A (±13.4 mA)
2.5
I
II
Differential
LDT
(ULVDS)
LVDS
Lightning Data Transport (HyperTransport™)
Logic
Low-Voltage Differential Signaling
2.5
N/A
Standard
Bus
Extended Mode
LVPECL
RSDS
HSTL
SSTL
Low-Voltage Positive Emitter-Coupled Logic
Reduced-Swing Differential Signaling
Differential High-Speed Transceiver Logic
Differential Stub Series Terminated Logic
2.5
2.5
1.8
2.5
N/A
N/A
II
II
LDT_25
LVDS_25
BLVDS_25
LVDSEXT_25
LVPECL_25
RSDS_25
DIFF_HSTL_II_18
DIFF_SSTL2_II
No
Yes
No
Yes
No
No
Yes
Yes
Symbol
(IOSTANDARD)
GTL
GTLP
HSTL_I
HSTL_III
HSTL_I_18
HSTL_II_18
HSTL_III_18
LVCMOS12
LVCMOS15
LVCMOS18
LVCMOS25
LVCMOS33
LVTTL
PCI33_3
SSTL18_I
SSTL18_II
SSTL2_I
SSTL2_II
DCI
Option
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
No
No
Yes
No
Yes
Yes
Notes:
1. 66 MHz PCI is not supported by the Xilinx IP core although PCI66_3 is an available I/O standard.
DS099-1 (v2.4) June 25, 2008
Product Specification
5
XILINX [ XILINX, INC ]
