eZ80F91 ASSP
Product Specification
48
GPIO Mode 1: Output
The port pin is configured as a standard digital output pin. The value written to the Port x
Data Register (Px_DR) is driven on the pin.
GPIO Mode 2: Input
The port pin is configured as a standard digital input pin. The output is high impedance.
The value stored in the Port x Data Register produces no effect. As in all modes, a read
from the Port x Data Register returns the pin’s value. GPIO Mode 2 is the default operat-
ing mode following a RESET.
GPIO Mode 3: Open Drain
The port pin is configured as open-drain Input/Output. The GPIO pins do not feature an
internal pull-up to the supply voltage. To employ the GPIO pin in OPEN-DRAIN Mode,
an external pull-up resistor must connect the pin to the supply voltage. Writing 0 to the
Port x Data Register outputs a Low at the pin. Writing 1 to the Port x Data Register results
in high-impedance output.
GPIO Mode 4: Open Source
The port pin is configured as open-source I/O. The GPIO pins do not feature an internal
pull-down to the supply ground. To employ the GPIO pin in OPEN-SOURCE Mode, an
external pull-down resistor must connect the pin to the supply ground. Writing 1 to the
Port x Data Register outputs a High at the pin. Writing 0 to the Port x Data Register results
in a high-impedance output.
GPIO Mode 5: Reserved
This mode, reserved for Zilog testing purposes, produces a high-impedance output.
GPIO Mode 6: Dual Edge-Triggered
The port pin is configured for dual edge-triggered interrupt mode. Both a rising and a fall-
ing edge on this pin cause an interrupt request to be sent to the CPU. To select this mode
from the default mode (Mode 2), observe the following brief procedure.
1. Set Px_DR = 1
2. Set Px_ALT2 = 1
3. Set Px_ALT1 = 0
4. Set Px_DDR = 0
Writing a 1 to the Port x ALT0 Register bit position corresponding to the interrupt request
clears the interrupt.
PS027004-0613
P R E L I M I N A R Y
General-Purpose Input/Output
ZILOG [ ZILOG, INC. ]
