eZ80F91 ASSP
Product Specification
52
Table 7. Port x Data Registers (Px_DR)
Bit
7
U
6
U
5
U
4
U
3
U
2
U
1
U
0
U
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
PA_DR = 0096h, PB_DR = 009Ah, PC_DR = 009Eh, PD_DR = 00A2h
Note: U = undefined; R/W = read/write.
Port x Data Direction Registers
In conjunction with the other GPIO Control registers, the Port x Data Direction registers
(see Table 8) control the operating modes of the GPIO port pins. For more details about
GPIO mode selection, see Table 6 on page 46.
Table 8. Port x Data Direction Registers (Px_DDR)
Bit
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
1
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
PA_DDR = 0097h, PB_DDR = 009Bh, PC_DDR = 009Fh, PD_DDR = 00A3h
Note: R/W = read/write.
Port x Alternate Register 0
The Port x Alternate Register 0 is used to clear edge-triggered interrupts. If an edge-trig-
gered interrupt occurs, writing 1 to the corresponding bit of this register will clear it.
Table 9. Port x Alternate Registers 0 (Px_ALT0)
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset
R/W
W
W
W
W
W
W
W
W
Address
Note: W = write only.
PA_ALT0 = 00A6h, PB_ALT0 = 00A7h, PC_ALT0 = 00CEh, PD_ALT0 = 00CFh
PS027004-0613
P R E L I M I N A R Y
General-Purpose Input/Output
ZILOG [ ZILOG, INC. ]
