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EZ80F91AZA50EG 参数 Datasheet PDF下载

EZ80F91AZA50EG图片预览
型号: EZ80F91AZA50EG
PDF下载: 下载PDF文件 查看货源
内容描述: [IC 8-BIT, FLASH, 50 MHz, MICROCONTROLLER, PQFP144, LEAD FREE, LQFP-144, Microcontroller]
分类和应用: 时钟微控制器外围集成电路
文件页数/大小: 395 页 / 1879 K
品牌: ZILOG [ ZILOG, INC. ]
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eZ80F91 ASSP  
Product Specification  
50  
request for falling edges. Writing 1 to the Port x Data Register bit sets the selected pin to  
generate an interrupt request for rising edges. The interrupt request remains active until 1  
is written to the corresponding bit of the Port x Alternate Register 0. To select Mode 9  
from the default mode (Mode 2), observe the following brief procedure.  
1. Set the Port x Data Register.  
2. Set Px_ALT2 = 1.  
3. Set Px_ALT1 = 1.  
4. Set Px_DDR = 1.  
GPIO Interrupts  
Each port pin is used as an interrupt source. Interrupts are either level- or edge-triggered.  
Level-Triggered Interrupts  
When the port is configured for level-triggered interrupts (Mode 8), the corresponding  
port pin is open-drain. An interrupt request is generated when the level at the pin is the  
same as the level stored in the Port x Data Register. The port pin value is sampled by the  
system clock. The input pin must be held at the selected interrupt level for a minimum of  
two clock periods to initiate an interrupt. The interrupt request remains active as long as  
this condition is maintained at the external source.  
For example, if PA3 is programmed for low-level interrupt and the pin is forced Low for  
two clock cycles, an interrupt request signal is generated from that port pin and sent to the  
CPU. The interrupt request signal remains active until the external device driving PA3  
forces the pin high. The CPU must be enabled to respond to interrupts for the interrupt  
request signal to be acted upon.  
Edge-Triggered Interrupts  
When the port is configured for edge-triggered interrupts, the corresponding port pin is  
open-drain. If the pin receives the correct edge from an external device, the port pin gener-  
ates an interrupt request signal to the CPU.  
When configured for dual edge-triggered interrupt mode (GPIO Mode 6), both a rising  
and a falling edge on the pin cause an interrupt request to be sent to the CPU. To select  
Mode 6 from the default mode (Mode 2), observe the following brief procedure.  
1. Set Px_DR = 1.  
2. Set Px_ALT2 = 1.  
3. Set Px_ALT1 = 0.  
PS027004-0613  
P R E L I M I N A R Y  
General-Purpose Input/Output