eZ80F91 ASSP
Product Specification
51
4. Set Px_DDR = 0.
When configured for single edge-triggered interrupt mode (GPIO Mode 9), the value in
the Port
x
Data Register determines whether a positive or negative edge causes an interrupt
request. 0 in the Port
x
Data Register bit sets the selected pin to generate an interrupt
request for falling edges. 1 in the Port
x
Data Register bit sets the selected pin to generate
an interrupt request for rising edges. To select Mode 9 from the default mode (Mode 2),
observe the following brief procedure.
1. Set Px_DR = 1
2. Set Px_ALT2 = 1
3. Set Px_ALT = 1.
4. Set Px_DDR = 1.
Edge-triggered interrupts are cleared by writing 1 to the corresponding bit of the Px_ALT0
Register. For example, if PD4 has been set up to generate an edge-triggered interrupt, the
interrupt is cleared by writing a 1 to Px_ALT0[4].
GPIO Control Registers
Each GPIO port has four registers that controls its operation. The operating mode of each
bit within a port is selected by writing to the corresponding bits of these four registers as
shown in
Data Direction Register (Px_DDR), Port Alternate Register 1 (PX_ALT1), and Port Alter-
nate Register 2 (Px_ALT2). In addition to these four control registers, each port has a Port
Alternate Register 0 (Px_ALT0), which is used for clearing edge-triggered interrupts.
Port x Data Registers
When the port pins are configured for one of the output modes, the data written to the Port
x
Data registers (see Table 7) is driven on the corresponding pins. In all modes, reading
from the Port
x
Data registers always returns the sampled current value of the correspond-
ing pins. When the port pins are configured for edge-triggered interrupts or level-sensitive
interrupts, the value written to the Port
x
Data Register bit selects the interrupt edge or
interrupt level (for more details about GPIO mode selection, see
PS027004-0613
PRELIMINARY
General-Purpose Input/Output
ZILOG [ ZILOG, INC. ]
