eZ80F91 ASSP
Product Specification
131
Bit
[5]
OC2
[4]
OC1
[3]
OC0
[2]
ICB
Description (Continued)
Output Compare 2
0: Output compare, OC2, does not occur.
1: Output compare, OC2, occurs.
Output Compare 1
0: Output compare, OC1, does not occur.
1: Output compare, OC1, occurs.
Output Compare 0
0: Output compare, OC0, does not occur.
1: Output compare, OC0, occurs.
Input Capture B
0: Input capture, ICB, does not occur. For Timer 1, the capture pin is IC1. For Timer 3, the
capture pin is IC3.
1: Input capture, ICB, occurs. For Timer 1, the capture pin is IC1. For Timer 3, the capture
pin is IC3.
Input Capture A
0: Input capture, ICA, or PWM power trip does not occur. For Timer 1, the capture pin is
IC0. For Timer 3, the capture pin is IC2.
1: Input capture, ICA, or PWM power trip occurs. For Timer 1, the capture pin is IC0. For
Timer 3, the capture pin is IC2.
End Of Count
0: End-of-count does not occur.
1: End-of-count occurs.
[1]
ICA
[0]
EOC
Timer Data Low Byte Register
The Timer
x
Data Low Byte Register returns the low byte of the current count value of the
selected timer. The Timer Data Low Byte Register, shown in Table 57, is read when the
timer is in operation. Reading the current count value does not affect timer operation. To
read the 16-bit data of the current count value, {TMRx_DR_H[7:0], TMRx_DR_L[7:0]},
first read the Timer Data Low Byte Register, followed by the Timer Data High Byte Reg-
ister. The Timer Data High Byte Register value is latched into temporary storage when a
read of the Timer Data Low Byte Register occurs.
This register shares its address with the corresponding timer reload register.
PS027004-0613
PRELIMINARY
Programmable Reload Timers
ZILOG [ ZILOG, INC. ]
