eZ80F91 ASSP
Product Specification
130
Bit
[2]
IRQ_ICB_EN
Description (Continued)
Interrupt Request Input Capture
x
Enable
0: Interrupt requests for ICx are disabled (valid only in INPUT CAPTURE Mode).
Timer 1: the capture pin is IC1.
Timer 3: the capture pin is IC3.
1: Interrupt requests for ICx are enabled (valid only in INPUT CAPTURE Mode).
For Timer 1: the capture pin is IC1.
For Timer 3: the capture pin is IC3.
Interrupt Request Input Capture/PWM Enable
0: Interrupt requests for ICA or PWM power trip are disabled (valid only in INPUT CAP-
TURE and PWM modes). For Timer 1: the capture pin is IC0. For Timer 3: the capture
pin is IC2.
1: Interrupt requests for ICA or PWM power trip are enabled (valid only in INPUT CAP-
TURE and PWM modes). For Timer 1: the capture pin is IC0. For Timer 3: the capture
pin is IC2.
[1]
IRQ_ICA_EN
[0]
Interrupt Request End Of Count Enable
IRQ_EOC_EN 0: Interrupt on end-of-count is disabled.
1: Interrupt on end-of-count is enabled.
Timer Interrupt Identification Register
The TImer
x
Interrupt Identification Register, shown in Table 56, is used to flag timer
events so that the CPU determines the cause of a timer interrupt. This register is cleared by
a CPU read.
Table 56. Timer Interrupt Identification Register (TMRx_IIR)
Bit
Field
Reset
R/W
Address
Note: R = read only;
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
2
0
R
1
0
R
0
0
R
TMR0_IIR = 0062h, TMR1_IIR = 0067h, TMR2_IIR = 0071h, TMR3_IIR = 0076h
Bit
[7]
[6]
OC3
Description
Reserved
This bit is unused and must be programmed to 0.
Output Compare 3
0: OC3 does not occur.
1: Output compare, OC3, occurs.
PS027004-0613
PRELIMINARY
Programmable Reload Timers
ZILOG [ ZILOG, INC. ]
