eZ80F91 ASSP
Product Specification
129
Timer Interrupt Enable Register
The Timer
x
Interrupt Enable Register, shown in Table 55, is used to control timer inter-
rupt operations. Only bits related to functions present in a given timer are active.
Table 55. Timer Interrupt Enable (TMRx_IER)
Bit
Field
Reset
R/W
Address
7
Reserved
0
R/W
0
R/W
6
5
4
3
2
IRQ_
ICB_EN
0
R/W
0
R/W
1
IRQ_
ICA_EN
0
R/W
0
IRQ_
EOC_EN
0
R/W
IRQ_OCx_EN
0
R/W
0
R/W
TMR0_IER = 0061h, TMR1_IER = 0066h, TMR2_IER = 0070h, TMR3_IER = 0075h
Note: R = read only; R/W = read/write.
Bit
[7]
Description
Reserved
This bit is unused and must be programmed to 0.
[6]
Interrupt Request Output Compare 3 Enable
IRQ_OC3_EN 0: Interrupt requests for OC3 are disabled (valid only in OUTPUT COMPARE Mode). OC
operations occur in Timer 3.
1: Interrupt requests for OC3 are enabled (valid only in OUTPUT COMPARE Mode). OC
operations occur in Timer 3.
[5]
Interrupt Request Output Compare 2 Enable
IRQ_OC2_EN 0: Interrupt requests for OC2 are disabled (valid only in OUTPUT COMPARE Mode). OC
operations occur in Timer 3.
1: Interrupt requests for OC2 are enabled (valid only in OUTPUT COMPARE Mode). OC
operations occur in Timer 3.
[4]
Interrupt Request Output Compare 1 Enable
IRQ_OC1_EN 0: Interrupt requests for OC1 are disabled (valid only in OUTPUT COMPARE Mode). OC
operations occur in Timer 3.
1: Interrupt requests for OC1 are enabled (valid only in OUTPUT COMPARE Mode). OC
operations occur in Timer 3.
[3]
Interrupt Request Output Compare 0 Enable
IRQ_OC0_EN 0: Interrupt requests for OC0 are disabled (valid only in OUTPUT COMPARE Mode). OC
operations occur in Timer 3.
1: Interrupt requests for OC0 are enabled (valid only in OUTPUT COMPARE Mode). OC
operations occur in Timer 3.
PS027004-0613
PRELIMINARY
Programmable Reload Timers
ZILOG [ ZILOG, INC. ]
