eZ80F91 ASSP
Product Specification
133
Timer Data High Byte Register
The Timer
x
Data High Byte Register, shown in Table 58, returns the high byte of the
count value of the selected timer as it existed at the time that the low byte was read. The
Timer Data High Byte Register is read when the timer is in operation. Reading the current
count value does not affect timer operation. To read the 16-bit data of the current count
value, {TMRx_DR_H[7:0], TMRx_DR_L[7:0]}, first read the Timer Data Low Byte Reg-
ister followed by the Timer Data High Byte Register. The Timer Data High Byte Register
value is latched into temporary storage when a read of the Timer Data Low Byte Register
occurs.
This register shares its address with the corresponding timer reload register.
Table 58. Timer Data High Byte Register (TMRx_DR_H)
Bit
Field
Reset
R/W
Address
Note: R = read only.
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
2
0
R
1
0
R
0
0
R
TMRx_DR_H
TMR0_DR_H = 0064h, TMR1_DR_H = 0069h,
TMR2_DR_H = 0073h, TMR3_DR_H = 0078h
Bit
[7:0]
TMR_DR_H
Description
Timer Data Low Byte
00h–FFh: These bits represent the high byte of the 2-byte timer data value,
{TMR
x
_DR_H[7:0], TMR
x
_DR_L[7:0]}. Bit 7 is bit 15 (msb) of the 16-bit timer data value.
Bit 0 is bit 8 of the 16-bit timer data value.
PS027004-0613
PRELIMINARY
Programmable Reload Timers
ZILOG [ ZILOG, INC. ]
