eZ80F91 ASSP
Product Specification
138
Timer Input Capture Value B High Byte Register
The Timer x Input Capture Value B High Byte Register, shown in Table 65, stores the high
byte of the capture value for external input B. For Timer 1, the external input is IC0. For
Timer 3, it is IC3.
Table 65. Timer Input Capture Value High Byte Register B (TMR1_CAPB_H, TMR3_CAPB_H)
Bit
7
6
5
4
3
2
1
0
Field
TMRx_CAPB_H
Reset
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R
Address
Note: R = read only.
TMR1_CAPB_H = 006Eh, TMR3_CAPB_H = 007Fh
Bit
Description
[7:0]
Timer Input Capture B High Byte
TMRx_CAPB_H 00h–FFh: These bits represent the high byte of the 2-byte capture value,
{TMRx_CAPB_H[7:0], TMRx_CAPB_L[7:0]}. Bit 7 is bit 15 (msb) of the 16-bit data
value. Bit 0 is bit 8 of the 16-bit timer data value.
Timer Output Compare Control Register 1
The Timer3 Output Compare Control Register 1, shown in Table 66, is used to select the
Master Mode and to provide initial values for the OC pins.
Table 66. Timer Output Compare Control Register 1 (TMR3_OC_CTL1)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
Reserved
OCx_INIT
MAST_MODE OC_EN
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
0080h
Note: R = read only; R/W = read/write.
Bit
Description
Reserved
[7:6]
These bits are unused and must be programmed to 00.
[5]
OC3_INIT
Output Compare 3 Initialize
0: OC pin cleared when initialized.
1: OC pin set when initialized.
PS027004-0613
P R E L I M I N A R Y
Programmable Reload Timers
ZILOG [ ZILOG, INC. ]
