eZ80F91 ASSP
Product Specification
139
Bit
[4]
OC2_INIT
[3]
OC1_INIT
[2]
OC0_INIT
Description (Continued)
Output Compare 2 Initialize
0: OC pin cleared when initialized.
1: OC pin set when initialized.
Output Compare 1 Initialize
0: OC pin cleared when initialized.
1: OC pin set when initialized.
Output Compare 0 Initialize
0: OC pin cleared when initialized.
1: OC pin set when initialized.
[1]
Master Mode Select
MAST_MODE 0: OC pins are independent.
1: OC pins all mimic OC0.
[0]
OC_EN
Output Compare Mode Enable
0: OUTPUT COMPARE Mode is disabled.
1: OUTPUT COMPARE Mode is enabled.
Timer Output Compare Control Register 2
The Timer3 Output Compare Control Register 2, shown in Table 67, is used to select the
event that occurs on the output compare pins when a timer compare happens.
Table 67. Timer Output Compare Control Register 2 (TMR3_OC_CTL2)
Bit
Field
Reset
R/W
Address
Note: R/W = read/write.
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
0081h
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
OC3_MODE
OC2_MODE
OC1_MODE
OC0_MODE
Bit
[7:6]
OC3_MODE
Description
Output Compare 3 Mode
00: Initialize OC pin to value specified in TMR3_OC_CTL1[OC3_INT].
01: OC pin is cleared upon timer compare.
10: OC pin is set upon timer compare.
11: OC pin toggles upon timer compare.
Output Compare 2 Mode
00: Initialize OC pin to value specified in TMR3_OC_CTL1[OC2_INT].
01: OC pin is cleared upon timer compare.
10: OC pin is set upon timer compare.
11: OC pin toggles upon timer compare.
[5:4]
OC2_MODE
PS027004-0613
PRELIMINARY
Programmable Reload Timers
ZILOG [ ZILOG, INC. ]
