eZ80F91 ASSP
Product Specification
140
Bit
[3:2]
OC1_MODE
Description (Continued)
Output Compare 1 Mode
00: Initialize OC pin to value specified in TMR3_OC_CTL1[OC1_INT].
01: OC pin is cleared upon timer compare.
10: OC pin is set upon timer compare.
11: OC pin toggles upon timer compare.
Output Compare 0 Mode
00: Initialize OC pin to value specified in TMR3_OC_CTL1[OC0_INT].
01: OC pin is cleared upon timer compare.
10: OC pin is set upon timer compare.
11: OC pin toggles upon timer compare.
[1:0]
OC0_MODE
Timer Output Compare Value Low Byte Register
The Timer3 Output Compare x Value Low Byte Register, shown in Table 68, stores the
low byte of the compare value for OC0–OC3.
Table 68. Compare Value Low Byte Register (TMR3_OCx_L)
Bit
Field
Reset
R/W
Address
Note: R/W = read/write.
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
TMR3_OC0_L = 0082h, TMR3_OC1_L = 0084h,
TMR3_OC2_L = 0086h, TMR3_OC3_L = 0088h
Bit
Description
[7:0]
Timer 3 Output Compare Low Byte
TMR3_OCx_L 00h–FFh: These bits represent the low byte of the 2-byte compare value,
{TMR3_OCx_H[7:0], TMR3_OCx_L[7:0]}. Bit 7 is bit 7 of the 16-bit data value. Bit 0 is bit
0 (lsb) of the 16-bit timer compare value.
PS027004-0613
PRELIMINARY
Programmable Reload Timers
ZILOG [ ZILOG, INC. ]
