eZ80F91 ASSP
Product Specification
136
Bit
Description (Continued)
Capture Edge Enable A
[1:0]
CAP_EDGE_A 00: Disable capture on ICA.
01: Enable capture only on the falling edge of ICA
10: Enable capture only on the rising edge of ICA.
11: Enable capture on both edges of ICA.
Timer Input Capture Value A Low Byte Register
The Timer x Input Capture Value A Low Byte Register, shown in Table 62, stores the low
byte of the capture value for external input A. For Timer 1, the external input is IC0. For
Timer 3, it is IC2.
Table 62. Timer Input Capture Value Low Byte Register A (TMR1_CAPA_L, TMR3_CAPA_L)
Bit
7
6
5
4
3
2
1
0
Field
TMRx_CAPA_L
Reset
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R
Address
Note: R = read only.
TMR1_CAPA_L = 006Bh, TMR3_CAPA_L = 007Ch
Bit
Description
[7:0]
Timer Input Capture A Low Byte
TMRx_CAPA_L 00h–FFh: These bits represent the low byte of the 2-byte capture value,
{TMRx_CAPA_H[7:0], TMRx_CAPA_L[7:0]}. Bit 7 is bit 7 of the 16-bit data value. Bit 0
is bit 0 (lsb) of the 16-bit timer data value.
PS027004-0613
P R E L I M I N A R Y
Programmable Reload Timers
ZILOG [ ZILOG, INC. ]
