eZ80F91 ASSP
Product Specification
144
Table 71. Example: Multi-PWM Addressing
Parameter
Timer Reload Value
PWM0 rising edge
PWM0 falling edge
PWM1 rising edge
PWM1 falling edge
PWM enable
PWM0 enable
PWM1 enable
Multi-PWM enable
Prescaler Divider = 4
PWM nonoverlapping delay = 0
Control Register(s)
{TMR3_RR_H, TMR3_RR_L}
{TMR3_PWM0R_H, TMR3_PWM0R_L}
{TMR3_PWM0F_H, TMR3_PWM0F_L}
{TMR3_PWM1R_H, TMR3_PWM1R_L}
{TMR3_PWM1F_H, TMR3_PWM1F_L}
TMR3_PWM_CTL1[PAIR_EN]
TMR3_PWM_CTL1[PWM0_EN]
TMR3_PWM_CTL1[PWM1_EN]
TMR3_PWM_CTL1[MPWM_EN]
TMR3_CTL[CLK_DIV]
TMR3_PWM_CTL2[PWM_DLY]
Value
000Ch
0008h
0004h
0006h
0007h
1
1
1
1
00b
0000b
PWM Master Mode
In PWM Master Mode, the pair of output signals generated from the PWM0 generator
(PWM0 and PWM0) are directed to all four sets of PWM output pairs. Setting
TMR3_PWM_CTL1[MM_EN] to 1 enables PWM Master Mode. Assuming the outputs
are all enabled and no AND/OR gating is used, all four PWM output pairs transition
simultaneously under the direction of PWM0 and PWM0. In PWM Master Mode, the out-
puts still be gated individually using the AND/OR gating functions described in the next
section. Multi-PWM Mode and the individual PWM outputs must be enabled along with
PWM Master Mode. It is possible to enable or disable any combination of the 4 PWM out-
puts while running in PWM Master Mode.
Modification of Edge Transition Values
Special circuitry is included for the update of the PWM edge transition values. Normal use
requires that these values be updated while the PWM generator is running.
Note:
Under certain circumstances, electric motors driven by the PWM logic encounters rough
operation. In other words, cycles could be skipped if the PWM waveform edge is not care-
fully modified.
PS027004-0613
PRELIMINARY
Programmable Reload Timers
ZILOG [ ZILOG, INC. ]
