eZ80F91 ASSP
Product Specification
148
Table 72. PWM Nonoverlapping Output Addressing (Continued)
Parameter
PWM0 enable
Multi-PWM enable
Control Register(s)
TMR3_PWM_CTL1[PWM0_EN]
TMR3_PWM_CTL1[MPWN_EN]
Value
1
1
Multi-PWM Power-Trip Mode
When enabled, the Multi-PWM power-trip feature forces the enabled PWM outputs to a
predetermined state when an interrupt is generated from an external source via IC0, IC1,
IC2, or IC3. One or multiple external interrupt sources are enabled at any given time. If
multiple sources are enabled, any of the selected external sources trigger an interrupt.
Configuring the PWM_CTL3 Register enables or disables interrupt sources. See
The possible interrupt sources for a Multi-PWM power-trip are:
•
•
•
•
IC0: digital input
IC1: digital input
IC2: digital input
IC3: digital input
When the power-trip is detected, TMR3_PWM_CTL3[PTD] is set to 1 to indicate detec-
tion of the power-trip. A value of 0 signifies that no power-trip is detected.
The PWMs are released only after a power-trip when TMR3_PWM_CTL3[PTD] is writ-
ten back to 0 by software. As a result, you are allowed to check the conditions of the motor
being controlled before releasing the PWMs. The explicit release also prevents noise
glitches after a power-trip from causing an accidental exit or reentry of the PWM power-
trip state.
The programmable power-trip states of the PWMs are globally grouped for the PWM out-
puts and the inverting PWM outputs. Upon detection of a power-trip, the PWM outputs
are forced to either a High state, a Low state, or high-impedance. The settings for the
power-trip states are made with power-trip control bits TMR3_PWM_CTL3[PT_LVL],
TMR3_PWM_CTL3[PT_LVL_N], and TMR3_PWM_CTL3[PT_TRI].
PS027004-0613
PRELIMINARY
Programmable Reload Timers
ZILOG [ ZILOG, INC. ]
