eZ80F91 ASSP
Product Specification
146
00
01
PWM0 Signal
PADR0
10
11
2
TMR3_PWM_CTL2[5:4]
PA0
PWM0 Output
00
01
PWM0 Signal
PADR4
10
11
2
TMR3_PWM_CTL2[7:6]
PA4
PWM0 Output
Figure 33. PWM AND/OR Gating Functional Diagram
If you enable the OR function on all PWM outputs and PADR0 is set to 1, then the PWM0
output on PA0 is forced High. Similarly, if you select the AND function on all PWM
outputs and PADR0 is set to a 0, then the PWM0 output on PA0 is forced Low.
PWM Nonoverlapping Output Pair Delays
A delay is added between the falling edge of the PWM (PWM) outputs and the rising edge
of the PWM (PWM) outputs. This delay is set to assure that even with load and output
drive variations there will be no overlap between the falling edge of a PWM (PWM) out-
put and the rising edge of its paired output. The selected delay is global to all four PWM
pairs. The delay duration is software-selectable using the 4-bit field,
TMR3_PWM_CTL2[PWM_DLY]. The duration is programmable in units of the system
clock (SCLK), from 0 SCLK periods to 15 SCLK periods. The
PS027004-0613
PRELIMINARY
Programmable Reload Timers
ZILOG [ ZILOG, INC. ]
