eZ80F91 ASSP
Product Specification
153
Pulse-Width Modulation Rising Edge Low Byte Register
A parallel 16-bit write of {TMR3_PWMxR_H[7–0], TMR3_PWMxR_L[7–0]} occurs
when software initiates a write to TMR3_PWMxR_L. See Table 76.
Table 76. PWMx Rising-Edge Low Byte Register (TMR3_PWMxR_L)
Bit
Field
Reset
R/W
Address
0
R/W
0
R/W
0
R/W
7
6
5
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
PWMxR_L
TMR3_PWM0R_L = 007Ch, TMR3_PWM1R_L = 007Eh,
TMR3_PWM2R_L = 0080h, TMR3_PWM3R_L = 0082h
Note: R/W = read/write;
x
indicates bits in the range [7:0].
Bit
[7:0]
PWMxR_L
Description
PWM Rising Edge Low Byte
00h–FFh: These bits represent the low byte of the 16-bit value to set the rising edge
COMPARE value for PWMx, {TMR3_PWMxR_H[7:0], TMR3_PWMxR_L[7:0]}. Bit 7 is bit
7 of the 16-bit timer data value. Bit 0 is bit 0 (lsb) of the 16-bit timer data value.
Pulse-Width Modulation Rising Edge High Byte Register
Writing to TMR3_PWMxR_H stores the value in a temporary holding register. A parallel
16-bit write of {TMR3_PWMxR_H[7–0], TMR3_PWMxR_L[7–0]} occurs when soft-
ware initiates a write to TMR3_PWMxR_L. See Table 77.
Table 77. PWMx Rising-Edge High Byte Register (TMR3_PWMxR_H)
Bit
Field
Reset
R/W
Address
0
R/W
0
R/W
0
R/W
7
6
5
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
PWMxR_H
TMR3_PWM0R_H = 007Dh, TMR3_PWM1R_H = 007Fh,
TMR3_PWM2R_H = 0081h, TMR3_PWM3R_H = 0083h
Note: R/W = read/write;
x
indicates bits in the range [7:0].
Bit
[7:0]
PWMxR_H
Description
PWM Rising Edge High Byte
00h–FFh: These bits represent the high byte of the 16-bit value to set the rising edge
COMPARE value for PWMx, {TMR3_PWMxR_H[7:0], TMR3_PWMxR_L[7:0]}. Bit 7 is bit
15 (msb) of the 16-bit timer data value. Bit 0 is bit 8 of the 16-bit timer data value.
PS027004-0613
PRELIMINARY
Programmable Reload Timers
ZILOG [ ZILOG, INC. ]
