eZ80F91 ASSP
Product Specification
150
Bit
Description (Continued)
Multi-PWM Mode Enable
[0]
MPWM_EN 0: Disable Multi-PWM Mode.
1: Enable Multi-PWM Mode.
Note: x indicates bits in the range [3:0].
Pulse-Width Modulation Control Register 2
The PWM Control Register 2, shown in Table 74, controls pulse-width modulation AND/
OR and edge delay functions.
Table 74. PWM Control Register 2 (PWM_CTL2)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
AON_EN
AO_EN
PWM_DLY
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
007Ah
Note: R/W = read/write.
Bit
Description
AND/OR Enable, Logic Low
[7:6]
AON_EN
00: Disable AND/OR features on PWM.
01: Enable AND logic on PWM.
10: Enable OR logic on PWM.
11: Disable AND/OR features on PWM.
[5:4]
AND/OR Enable
AO_EN
00: Disable AND/OR features on PWM.
01: Enable AND logic on PWM.
10: Enable OR logic on PWM.
11: Disable AND/OR features on PWM.
PS027004-0613
P R E L I M I N A R Y
Programmable Reload Timers
ZILOG [ ZILOG, INC. ]
