eZ80F91 ASSP
Product Specification
149
Multi-PWM Control Registers
This section describes the following PWM control registers:
Pulse-Width Modulation Control Register 1
The PWM Control Register 1 (see Table 73) controls the enabling of PWM functions.
Table 73. PWM Control Register 1 (PWM_CTL1)
Bit
Field
Reset
R/W
Address
Note: R/W = read/write.
7
PAIR_EN
0
R/W
6
PT_EN
0
R/W
5
MM_EN
0
R/W
4
0
R/W
0079h
3
0
R/W
2
0
R/W
1
0
R/W
0
MPWM_EN
0
R/W
PWMx_EN
Bit
[7]
PAIR_EN
[6]
PT_EN
[5]
MM_EN
[4:1]
PWMx_EN
Description
PWM Output Pair Enable
0: Global disable of the PWM outputs (PWM outputs enabled only).
1: Global enable of the PWM and PWM output pairs.
PWM Power Trip Enable
0: Disable power-trip feature.
1: Enable power-trip feature.
PWM Master Mode Enable
0: Disable Master Mode.
1: Enable Master Mode.
PWM Generator
x
Enable
0: Disable PWM generator 3, 2, 1, 0.
1: Enable PWM generator 3, 2, 1, 0.
Note:
x
indicates bits in the range [3:0].
PS027004-0613
PRELIMINARY
Programmable Reload Timers
ZILOG [ ZILOG, INC. ]
