eZ80F91 ASSP
Product Specification
152
Pulse-Width Modulation Control Register 3
The PWM Control Register 3 (see Table 75) is used to configure the PWM power trip
functionality.
Table 75. PWM Control Register 3 (PWM_CTL3)
Bit
Field
Reset
R/W
Address
0
R/W
7
6
0
R/W
5
0
R/W
4
0
R/W
3
PT_TRI
0
R/W
007Bh
2
PT_LVL
0
R/W
1
PT_LVL_N
0
R/W
0
PTD
0
R
PT_ICx_EN
Note:
x
indicates bits in the range [3:0]; R/W = read/write; R = read only.
Bit
[7]
PT_IC3_EN
[6]
PT_IC2_EN
[5]
PT_IC1_EN
[4]
PT_IC0_EN
[3]
PT_TRI
[2]
PT_LVL
[1]
PT_LVL_N
[0]
PTD
Description
IC3 Power Trip Enable
0: Power trip disabled on IC3.
1: Power trip enabled on IC3.
IC2 Power Trip Enable
0: Power trip disabled on IC2.
1: Power trip enabled on IC2.
IC1 Power Trip Enable
0: Power trip disabled on IC1.
1: Power trip enabled on IC1.
IC0 Power Trip Enable
0: Power trip disabled on IC0.
1: Power trip enabled on IC0.
PWM Trip Level
0: All PWM trip levels are open-drain
1: All PWM trip levels are defined by PT_LVL and PT_LVL_N
PWMx Level Output
0: After power trip, PWMx outputs are set to one.
1: After power trip, PWMx outputs are set to zero.
PWMx Level Output, Logic Low
0: After power trip, PWMx outputs are set to one.
1: After power trip, PWMx outputs are set to zero.
Power Trip Event
0: Power trip has been cleared.
1: This bit is set after power trip event.
PS027004-0613
PRELIMINARY
Programmable Reload Timers
ZILOG [ ZILOG, INC. ]
