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产品型号CDCLVC1104PW的概述

CDCLVC1104PW 概述 CDCLVC1104PW 是德州仪器（Texas Instruments）出品的一款高性能时钟分配芯片。该芯片设计目标是为现代高速数字电路提供稳定、低抖动的时钟信号，其广泛应用于网络通信、存储器接口、消费电子等领域。由于其优良的性能指标，CDCLVC1104PW 已成为许多电子设计工程师的首选元件。详细参数 CDCLVC1104PW 的主要参数如下： - 电源电压：3.3V，提供了一个广泛的工作电压范围，以便于与多种逻辑电平兼容。 - 工作温度范围：-40°C 至 +85°C，适合在恶劣环境下使用。 - 输出频率范围：最大可支持的输出频率为 200MHz，适合多种高速应用。 - 时钟抖动：由于其独特的设计，CDCLVC1104PW 的随机抖动小于 1 ps RMS，确保信号的完整性。 - 输入电压范围：从 0V 到 Vin 供电电压，输入信号兼容 LV...

产品型号CDCLVC1104PW的Datasheet PDF文件预览

CDCLVC11xx

www.ti.com

SCAS895 –MAY 2010

3.3 V and 2.5 V LVCMOS High-Performance Clock Buffer Family

Check for Samples: CDCLVC11xx

FEATURES

•

Operating Temperature Range: –40°C to 85°C

•

High-Performance 1:2, 1:3, 1:4, 1:6, 1:8, 1:10,

1:12 LVCMOS Clock Buffer Family

Available in 8-, 14-, 16-, 20-, 24-Pin TSSOP

Package (all pin compatible)

•

Very Low Pin-to-Pin Skew < 50 ps

Very Low Additive Jitter < 100 fs

Supply Voltage: 3.3 V or 2.5 V

f_max= 250 MHz for 3.3 V

APPLICATIONS

•

General Purpose Communication, Industrial

and Consumer Applications

f_max= 180 MHz for 2.5 V

CLKIN

24 Y1

23 Y3

22 VDD

21 Y2

20 GND

19 Y5

18 VDD

17 Y7

16 Y8

15 GND

14 Y10

13 VDD

CMOS

CLKIN

CDCLVC 1102

CDCLVC 1103

CDCLVC 1104

CMOS

GND

VDD

CMOS

CDCLVC 1106

CDCLVC 1108

GND

CMOS

VDD

CDCLVC 1110

CDCLVC 1112

Y9 10

GND 11

Y11 12

•

CMOS

DESCRIPTION

The CDCLVC11xx is a modular, high-performance, low-skew, general purpose clock buffer family from Texas

Instruments.

The whole family is designed with a modular approach in mind. It is intended to round up TI's series of LVCMOS

clock generators.

There are 7 different fan-out variations, 1:2 to 1:12, available. All of the devices are pin compatible to each other

for easy handling.

All family members share the same high performing characteristics like low additive jitter, low skew, and wide

operating temperature range.

The CDCLVC11xx supports an asynchronous output enable control (1G) which switches the outputs into a low

state when 1G is low. Also, versions with synchronized enable control for glitch free switching and three-state

outputs are planned in future device options.

The CDCLVC11xx operate in a 2.5 V and 3.3 V environment and are characterized for operation from –40°C to

85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

CDCLVC11xx

SCAS895 –MAY 2010

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

PACKAGE OPTIONS

CLKIN

Y 1

CLKIN

14 Y 1

13 Y 3

12 VDD

11 Y 2

10 GND

CLKIN

20 Y1

19 Y3

18 VDD

17 Y2

16 GND

15 Y5

CDCLVC1102

Y 0

VDD

Y 0

CDCLVC1106

GND

VDD

Y 4

GND

VDD

Y 4

CDCLVC 1110

Y 5

CLKIN

Y 1

GND

VDD

GND

Y 6

14 VDD

13 Y7

CDCLVC1103

Y 0

VDD

Y 2

VDD

12 Y8

GND

CLKIN

16 Y 1

15 Y 3

Y 9 10

11 GND

Y 0

GND

VDD

Y 4

14 VDD

13 Y 2

CLKIN

Y 1

CLKIN

24 Y1

CDCLVC1108

Y 3

Y 0

23 Y3

CDCLVC1104

12 GND

11 Y 5

Y 0

VDD

Y 2

22 VDD

21 Y2

GND

VDD

Y 4

GND

Y 6

10 VDD

20 GND

19 Y5

Y 7

CDCLVC 1112

GND

Y 6

18 VDD

17 Y7

VDD

16 Y8

Y 9 10

GND 11

Y11 12

15 GND

14 Y10

13 VDD

PIN FUNCTIONS

LVCMOS

CLOCK INPUT

CLOCK OUTPUT

ENABLE

SUPPLY

VOLTAGE

LVCMOS CLOCK OUTPUT

GROUND

DEVICES

CLKIN

Y0, Y1, … Y11

3, 8

V_DD

GND

CDCLVC1102

CDCLVC1103

CDCLVC1104

CDCLVC1106

CDCLVC1108

CDCLVC1110

CDCLVC1112

3, 8, 5

3, 8, 5, 7

3, 14, 11, 13, 6, 9

5, 8, 12

5, 10, 14

5, 9, 14, 18

5, 9, 13, 18, 22

4, 7, 10

4, 7, 12

4, 7, 11, 16

4, 7, 11, 15, 20

3, 16, 13, 15, 6, 11, 8, 9

3, 20, 17, 19, 6, 15, 8, 13, 10

3, 24, 21, 23, 6, 19, 8, 17, 16, 10, 14, 12

OUTPUT LOGIC TABLE

INPUTS

OUTPUTS

CLKIN

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Product Folder Link(s): CDCLVC11xx

CDCLVC11xx

www.ti.com

SCAS895 –MAY 2010

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

VALUE / UNIT

V_DD

V_IN

V_O

I_IN

Supply voltage range

–0.5 V to 4.6 V

–0.5 V to V_DD+ 0.5 V

±20 mA

(2)

Input voltage range

Output voltage range

Input current

(2)

I_O

Continuous output current

Maximum junction temperature

Storage temperature range

±50 mA

T_J

125°C

T_ST

–65°C to 150°C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) This value is limited to 4.6 V maximum.

THERMAL INFORMATION

DCDLVC1102/03/04

CDCLVC1106

CDCLVC1108 CDCLVC11010 CDCLVC1112

THERMAL METRIC⁽¹⁾

8 PINS

149.4

69.4

16 PINS

108.4

33.6

20 PINS

83.0

24 PINS

87.9

UNITS

14 PINS

112.6

q_JA

Junction-to-ambient thermal resistance⁽²⁾

°C/W

(3)

q_JC(top)Junction-to-case(top) thermal resistance

48.0

32.3

26.5

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific

JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN

3.0

NOM

3.3

MAX

3.6

UNIT

3.3 V supply

V_DD

Supply voltage range

Low-level input voltage

High-level input voltage

2.5 V supply

2.3

2.5

2.7

V_DD= 3.0 V to 3.6 V

V_DD= 2.3 V to 2.7 V

V_DD= 3.0 V to 3.6 V

V_DD= 2.3 V to 2.7 V

V_DD= 2.3 V to 3.6 V

V_DD/2 – 600

V_DD/2 – 400

V_IL

V_DD/2 + 600

V_DD/2 + 400

V_IH

V_th

Input threshold voltage

Input slew rate

V_DD/2

t_r/ t_f

1.8

V/ns

V_DD= 3.0 V to 3.6 V

V_DD= 2.3 V to 2.7 V

V_DD= 3.0 V to 3.6 V

V_DD= 2.3 V to 2.7 V

Minimum pulse width at

CLKIN

t_w

2.75

250

180

LVCMOS clock Input

Frequency

f_CLK

T_A

MHz

°C

Operating free-air temperature

–40

Submit Documentation Feedback

Product Folder Link(s): CDCLVC11xx

CDCLVC11xx

SCAS895 –MAY 2010

www.ti.com

DEVICE CHARACTERISTICS

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

CONDITION

MIN TYP⁽¹⁾

MAX UNIT

OVERALL PARAMETERS FOR ALL VERSIONS

1G = V_DD; CLKIN = 0 V or V_DD; I_O= 0 mA; V_DD= 3.6 V

1G = V_DD; CLKIN = 0 V or V_DD; I_O= 0 mA; V_DD= 2.7 V

1G = 0 V; CLKIN = 0 V or V_DD; I_O= 0 mA; V_DD= 3.6 V or 2.7 V

V_DD= 3.3 V; f = 10 MHz

10 mA

I_DD

I_PD

Static device current⁽²⁾

Power down current

µA

Power dissipation capacitance

per output⁽³⁾

C_PD

V_DD= 2.5 V; f = 10 MHz

4.5

Input leakage current at 1G

± 8

I_I

V_I= 0 V or V_DD, V_DD= 3.6 V or 2.7 V

µA

Input leakage current at CLKIN

± 25

V_DD= 3.3 V

R_OUTOutput impedance

f_OUTOutput frequency

V_DD= 2.5 V

V_DD= 3.0 V to 3.6 V

V_DD= 2.3 V to 2.7 V

250 MHz

180 MHz

OUTPUT PARAMETERS FOR V_DD= 3.3 V ± 0.3 V

V_DD= 3 V, I_OH= –0.1 mA

2.9

2.5

2.2

V_OHHigh-level output voltage

V_DD= 3 V, I_OH= –8 mA

V_DD= 3 V, I_OH= –12 mA

V_DD= 3 V, I_OL= 0.1 mA

V_DD= 3 V, I_OL= 8 mA

V_DD= 3 V, I_OL= 12 mA

0.1

V_OLLow-level output voltage

0.5

0.8

t_PLH

t_PHL

Propagation delay

CLKIN to Yn

0.8

0.3

2.0

t_sk(o)Output skew

Equal load of each output

0.8

t_r/t_f

t_DIS

t_EN

Rise and fall time

20%–80% (V_OH- V_OL

)

Output disable time

Output enable time

Pulse skew ;

1G to Yn

t_sk(p)

To be measured with input duty cycle of 50%

180

(4)

t_PLH(Yn)– t_PHL(Yn)

t_sk(pp)Part-to-part skew

t_jitterAdditive jitter rms

Under equal operating conditions for two parts

12kHz…20 MHz, f_OUT= 250 MHz

0.5

100

(1) All typical values are at respective nominal V_DD. For switching characteristics, outputs are terminated to 50 Ω to V_DD/2 (see Figure 1).

(2) For dynamic I_DDover frequency see Figure 8 and Figure 9.

(3) This is the formula for the power dissipation calculation (see Figure 8 and the Power Consideration section).

P_tot= P_stat+ P_dyn+ P_Cload[W]

P_stat= V_DD× I_DD[W]

P_dyn= C_PD× V_DD2 × ƒ [W]

P_Cload= C_load× V_DD2 × ƒ × n [W]

n = Number of switching output pins

(4) t_sk(p)depends on output rise- and fall-time (t_r/t_f). The output duty-cycle can be calculated: odc = (t_w(OUT)± t_sk(p))/t_period; t_w(OUT)is

pulse-width of output waveform and tperiod is 1/f_OUT

Submit Documentation Feedback

Product Folder Link(s): CDCLVC11xx

CDCLVC11xx

www.ti.com

SCAS895 –MAY 2010

DEVICE CHARACTERISTICS (continued)

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

CONDITION

MIN TYP⁽¹⁾

MAX UNIT

OUTPUT PARAMETERS FOR V_DD= 2.5 V ± 0.2 V

V_DD= 2.3 V, I_OH= –0.1 mA

2.2

1.7

V_OHHigh-level output voltage

V_OLLow-level output voltage

V_DD= 2.3 V, I_OH= –8 mA

V_DD= 2.3 V, I_OL= 0.1 mA

V_DD= 2.3 V, I_OL= 8 mA

0.1

0.5

t_PLH

t_PHL

Propagation delay

CLKIN to Yn

1.0

0.3

2.6

t_sk(o)Output skew

Equal load of each output

20%–80% reference point

1G to Yn

1.2

t_r/t_f

t_DIS

t_EN

Rise and fall time

Output disable time

Output enable time

Pulse skew ;

1G to Yn

t_sk(p)

To be measured with input duty cycle of 50%

220

(5)

t_PLH(Yn)– t_PHL(Yn)

t_sk(pp)Part-to-part skew

t_jitterAdditive jitter rms

Under equal operating conditions for two parts

12kHz…20 MHz, f_OUT= 180 MHz

1.2

350

(5) t_sk(p)depends on output rise- and fall-time (t_r/t_f). The output duty-cycle can be calculated: odc = (t_w(OUT)± t_sk(p))/t_period; t_w(OUT)is

pulse-width of output waveform and tperiod is 1/f_OUT

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Product Folder Link(s): CDCLVC11xx

CDCLVC11xx

SCAS895 –MAY 2010

www.ti.com

PARAMETERS MEASUREMENT INFORMATION

= 3.3 V or 2.5 V

LVCMOS

Output

= 50 W

R=50 W

C = 2 pF

from Measurement Equipment

parasitic capasitance

Figure 1. Test Load Circuit

= 3.3 V or 2.5 V

R=100 W

LVCMOS

Output

= 50 W

parasitic input capacitance

R= 100 W

Figure 2. Application Load With 50 Ω Line Termination

= 3.3 V or 2.5 V

RS = 10 W (V = 3.3 V)

RS = 0 W (V = 2.5 V)

LVCMOS

Output

= 50 W

parasitic input capacitance

Figure 3. Application Load With Series Line Termination

V_DD/ 2

V_IN/ 2

1 G

V_IN/ 2

V_DD/ 2

n+1

t_sk(o)

t_DIS

t_EN

t_sk(o)

Figure 4. t_DISand t_ENfor Disable Low

Figure 5. Output Skew t_sk(o)

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Product Folder Link(s): CDCLVC11xx

CDCLVC11xx

www.ti.com

SCAS895 –MAY 2010

PARAMETERS MEASUREMENT INFORMATION (continued)

/ 2

CLKIN

80 % V

20 % V

-V

OH OL

/ 2

-V

OH OL

PLH

PHL

Note: t

= | t

– t

PHL

sk(p)

PLH

Figure 6. Pulse Skew t_sk(p)and Propagation Delay

t_PLH/t_PHL

Figure 7. Rise/Fall Times t_r/t_f

TYPICAL CHARACTERISTICS

Power Consideration

The following power consideration refers to the device-consumed power consumption only. The device power

consumption is the sum of static power and dynamic power. The dynamic power usage consists of two

components:

1. Power used by the device as it switches states.

2. Power required to charge any output load.

The output load can be capacitive only or capacitive and resistive. The following formula and the power graphs in

Figure 8 and Figure 9 can be used to obtain the power consumption of the device:

P_dev= P_stat+ n (P_dyn+ P_Cload

)

P_stat= V_DDx I_DD

P_dyn+ P_Cload= see Figure 8 and Figure 9

where:

V_DD= Supply voltage (3.3 V or 2.5 V)

I_DD= Static device current (typ 6 mA for V_DD= 3.3 V; typ 3 mA for V_DD= 2.5 V)

n = Number of switching output pins

Example for Device Power Consumption for CDCLVC1104: 4 outputs are switching, f = 120 MHz, V_DD= 3.3 V

and C_load= 2 pF per output:

P_dev= P_stat+ n (P_dyn+ P_Cload) = 19.8 mW + 40 mW = 59.8 mW

P_stat= V_DDx I_DD= 6 mA x 3.3 V = 19.8 mW

n (P_dyn+ P_Cload) = 4 x 10 mW = 40 mW

NOTE

For dimensioning the power supply, the total power consumption needs to be considered.

The total power consumption is the sum of the device power consumption and the power

consumption of the load.

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Product Folder Link(s): CDCLVC11xx

CDCLVC11xx

SCAS895 –MAY 2010

www.ti.com

TYPICAL CHARACTERISTICS (continued)

= 3.3 V

+ P

Cload8pF

= 2.5 V

dyn

+ P

Cload8pF

dyn

+ P

Cload50/2

dyn

+ P

Cload50/2

dyn

+ P

Cload2pF

+ P

Cload2pF

dyn

60 80 100 120 140 160 180

f - Clock Frequency - MHz

20 40 60 80 100 120 140 160 180 200 220 240

f - Clock Frequency - MHz

Figure 8. Device Power Consumption vs Clock Frequency

Figure 9. Device Power Consumption vs Clock Frequency

(Load 50Ω into V_DD/2. 2pF, 8pF; Per Output)

= 2.5 V

= 3.3 V

= C * V

* f

dyn

= C * V

* f

dyn

f - Clock Frequency - MHz

80 100 120 140 160 180

20 40 60 80 100 120 140 160 180 200 220 240

f - Clock Frequency - MHz

Figure 10. Dynamic Supply Current vs Clock Frequency

(C_PD= 6pF, No Load; Per Output)

Figure 11. Dynamic Supply Current vs Clock Frequency

(C_PD= 4.5pF, No Load; Per Output)

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PACKAGE OPTION ADDENDUM

www.ti.com

26-Jun-2010

PACKAGING INFORMATION

Status ⁽¹⁾

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

CDCLVC1102PW

CDCLVC1102PWR

CDCLVC1103PW

CDCLVC1103PWR

CDCLVC1104PW

CDCLVC1104PWR

CDCLVC1106PW

CDCLVC1106PWR

CDCLVC1108PW

CDCLVC1108PWR

CDCLVC1110PW

CDCLVC1110PWR

CDCLVC1112PW

CDCLVC1112PWR

ACTIVE

TSSOP

150

2000

150

2000

150

2000

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

Purchase Samples

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

Purchase Samples

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Request Free Samples

Purchase Samples

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Request Free Samples

Purchase Samples

Green (RoHS

& no Sb/Br)

2000

Green (RoHS

& no Sb/Br)

Request Free Samples

Purchase Samples

Green (RoHS

& no Sb/Br)

2000

Green (RoHS

& no Sb/Br)

Request Free Samples

Purchase Samples

Green (RoHS

& no Sb/Br)

2000

Green (RoHS

& no Sb/Br)

Request Free Samples

Purchase Samples

Green (RoHS

& no Sb/Br)

2000

Green (RoHS

& no Sb/Br)

Request Free Samples

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

26-Jun-2010

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

30-Jul-2010

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

CDCLVC1102PWR

CDCLVC1103PWR

CDCLVC1104PWR

CDCLVC1106PWR

CDCLVC1108PWR

CDCLVC1110PWR

CDCLVC1112PWR

TSSOP

2000

330.0

12.4

16.4

7.0

3.6

5.6

7.1

8.3

1.6

8.0

12.0

16.0

7.0

6.9

6.95

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

30-Jul-2010

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

CDCLVC1102PWR

CDCLVC1103PWR

CDCLVC1104PWR

CDCLVC1106PWR

CDCLVC1108PWR

CDCLVC1110PWR

CDCLVC1112PWR

TSSOP

2000

346.0

29.0

33.0

Pack Materials-Page 2

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30

0,19

0,10

0,65

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

0°–8°

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

9,80

9,60

A MAX

A MIN

7,70

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

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CDCLVC1104PW产品参数

型号:	CDCLVC1104PW
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	TEXAS INSTRUMENTS INC
零件包装代码：	TSSOP
包装说明：	TSSOP-8
针数：	8
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	6 weeks
风险等级：	1.33
Samacsys Description：	Low Jitter, 1:4 LVCMOS Fan-out Clock Buffer
系列：	CDC
输入调节：	STANDARD
JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e4
长度：	3 mm
逻辑集成电路类型：	LOW SKEW CLOCK DRIVER
最大I（ol）：	0.012 A
湿度敏感等级：	1
功能数量：	1
反相输出次数：
端子数量：	8
实输出次数：	1
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP
封装等效代码：	TSSOP8,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
包装方法：	TUBE
峰值回流温度（摄氏度）：	260
电源：	3.3 V
Prop。Delay @ Nom-Sup：	2 ns
传播延迟（tpd）：	2.6 ns
认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.05 ns
座面最大高度：	1.2 mm
子类别：	Clock Driver
最大供电电压 (Vsup)：	2.7 V
最小供电电压 (Vsup)：	2.3 V
标称供电电压 (Vsup)：	2.5 V
表面贴装：	YES
技术：	CMOS
温度等级：	INDUSTRIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	0.65 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	4.4 mm
最小 fmax：	250 MHz

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