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产品型号HI5780的Datasheet PDF文件预览

HI5780  
10-Bit, 80 MSPS, High Speed,  
Low Power D/A Converter  
August 1997  
Features  
Description  
[ /Title  
(HI578  
0)  
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . 80 MSPS The HI5780 is a 10-bit, 80 MSPS, high speed, low power  
CMOS D/A converter. The converter incorporates a 10-bit input  
data register with current outputs. The HI5780 includes a power  
• Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150mW  
/Sub-  
ject  
(10-  
Bit, 80  
MSPS,  
High  
Speed,  
Low  
Power  
D/A  
Con-  
verter)  
/Autho  
r ()  
/Key-  
words  
(Inter-  
sil  
down feature that reduces power consumption and a blanking  
control. The on-chip bandgap reference can be used to set the  
output current range of the D/A.  
• Differential Linearity Error . . . . . . . . . . . . . . . ±0.5 LSB  
• TTL/CMOS Compatible Inputs  
• Built in Bandgap Voltage Reference  
Ordering Information  
• Power Down and Blanking Control Pins  
• Direct Replacement for Sony CXD2306  
PART  
NUMBER  
TEMP.  
o
RANGE ( C)  
-20 to 75  
25  
PACKAGE  
32 Ld MQFP  
Evaluation Kit  
PKG. NO.  
Applications  
HI5780JCQ  
HI5780-EV  
Q32.7x7-S  
• Wireless Communications  
• Direct Digital Frequency Synthesis  
• Signal Reconstruction  
• Test Equipment  
• High Resolution Imaging and Graphics Systems  
• Arbitrary Waveform Generators  
Pinout  
Corpo-  
ration,  
Semi-  
con-  
HI5780  
(MQFP)  
ductor  
Com-  
muni-  
cations  
Divi-  
sion,  
Inter-  
sil  
Semi-  
con-  
32 31 30 29 28 27 26 25  
D3  
1
2
3
4
5
6
7
8
24  
IOUT  
D4  
D5  
23  
22  
21  
20  
19  
18  
17  
IOUT  
VG  
D6  
AVDD  
AVDD  
VREF  
REFOUT  
IREF  
D7  
D8  
D9 (MSB)  
NC  
9
10 11 12 13 14 15 16  
ductor,  
Com-  
mLink,  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 4024.4  
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999  
10-1716  
HI5780  
Typical Application Circuit  
+5V  
+5V  
HI5780  
0.01µF  
0.01µF  
(20, 21) AVDD  
(22) VG  
DVDD (13, 28)  
0.1µF  
D9  
D9 (MSB) (7)  
D8 (6)  
D8  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D7 (5)  
(18) REFOUT  
(19) VREF  
D6 (4)  
D5 (3)  
0.1µF  
(14) VB  
D4 (2)  
D3 (1)  
D/A OUT  
(24) IOUT  
(23) IOUT  
D2 (32)  
D1 (31)  
D0 (30)  
200Ω  
D0  
CLK (9)  
(17) IREF  
BLK (10)  
50Ω  
2.0kΩ  
DGND (8, 12,15, 16,  
26, 27, 29)  
(25) AGND  
PD (11)  
POWER DOWN CONTROL  
Functional Block Diagram  
IOUT  
(LSB) D0  
D1  
4 LSB  
CURRENT  
CELLS  
D2  
D3  
IOUT  
D4  
DATA  
REGISTER  
D5  
D6  
DECODER  
DECODER  
6 MSB  
CURRENT  
CELLS  
D7  
D8  
VG  
(MSB) D9  
VREF  
IREF  
-
+
CURRENT CELLS  
(FOR FULL SCALE)  
BLK  
CLK  
CLOCK  
GENERATOR  
BIAS VOLTAGE  
GENERATOR  
VB  
PD  
BANDGAP  
VOLTAGE  
REFOUT  
REFERENCE  
10-1717  
HI5780  
Absolute Maximum Ratings  
Thermal Information  
o
Supply Voltage V to DGND . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V  
Thermal Resistance (Typical, Note 1)  
θ
( C/W)  
DD  
JA  
Digital Input Voltages (D9-D0, CLK, BLANK, PD) . . . . V to -0.5V  
Internal Reference Output Current . . . . . . . . . . . . . . . . . . . . ±2.5mA  
DD  
MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Maximum Junction Temperature (Plastic Package)  
Maximum Storage Temperature Range . . . . . . . . . . -65 C to 150 C  
122  
o
o
Reference Input Voltage Range (V  
) . . . . . . . . . . . . V to -0.5 V  
REF  
DD  
o
Analog Output Current (I  
). . . . . . . . . . . . . . . . . . . . . . . . . .15mA  
OUT  
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300 C  
(MQFP - Lead Tips Only)  
Operating Conditions  
o
o
Temperature Range, HI5780BIx. . . . . . . . . . . . . . . . . -20 C to 75 C  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation  
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTE:  
1. θ is measured with the component mounted on an evaluation PC board in free air.  
JA  
Electrical Specifications AV , DV = 5.00V, V  
= 2.0V, f  
= 80 MSPS, R  
= 200Ω, R  
= 3.3k,  
REF  
DD  
T = 25 C  
DD  
REF  
CLK  
LOAD  
o
A
HI5780JCQ  
TYP  
PARAMETER  
SYSTEM PERFORMANCE  
Resolution  
TEST CONDITIONS  
MIN  
MAX  
UNITS  
10  
-2.0  
-0.5  
-
-
-
Bits  
LSB  
LSB  
µA  
Integral Linearity Error, INL  
Differential Linearity Error, DNL  
(Notes 4, 5) (“Best Fit” Straight Line)  
(Notes 4, 5)  
1.25  
0.25  
-
2.0  
0.5  
5
Offset Error, I  
(Notes 4, 5)  
OS  
Full Scale Output Current, I  
(Note 4)  
9.0  
-
9.6  
0.26  
1.92  
10  
-
mA  
FS  
o
Full Scale Drift Coefficient, I  
(Note 2)  
mV/ C  
DRIFT  
Output Voltage Compliance Range  
DYNAMIC CHARACTERISTICS  
Throughput Rate  
(Note 3), 10-Bit Accuracy  
1.8  
2.0  
V
(Note 3)  
80.0  
-
-
-
-
MSPS  
ns  
Output Voltage Full Scale Step  
To ±0.5 LSB Error Band R = 75, 10-Bit Accuracy  
6.0  
L
Settling Time, t  
(Note 3)  
SETT FS  
Singlet Glitch Area, GE (Peak)  
Differential Gain, DG  
R
= 75Ω, V  
= 1.0V (Note 3)  
P-P  
-
-
-
-
40  
2.5  
-
-
-
-
pV-s  
%
LOAD  
OUT  
(Note 4)  
(Note 4)  
Differential Phase, DP  
1.3  
Degrees  
dBc  
Spurious Free Dynamic Range,  
SFDR to Nyquist  
f
= 40 MSPS, f  
= 2.02MHz, 20MHz Span  
= 2.02MHz, 40MHz Span  
OUT  
48.5  
CLK  
OUT  
(Note 3)  
f
= 80 MSPS, f  
-
47.5  
-
dBc  
CLK  
(Note 3)  
f
f
= 40 MSPS, f  
= 80 MSPS, f  
= 10MHz, 20MHz Span (Note 3)  
= 20MHz, 40MHz Span (Note 3)  
= 2.02MHz, 2MHz Span (Note 3)  
= 2.02MHz, 2MHz Span (Note 3)  
-
-
-
-
-
-
40.75  
38.5  
75.0  
73.5  
56.5  
49.0  
-
-
-
-
-
-
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
CLK  
CLK  
OUT  
OUT  
OUT  
OUT  
Spurious Free Dynamic Range, SFDR Within  
a Window  
f
= 40 MSPS, f  
= 80 MSPS, f  
CLK  
f
CLK  
f
= 40 MSPS, f  
= 80 MSPS, f  
= 10MHz, 2MHz Span (Note 3)  
= 20MHz, 2MHz Span (Note 3)  
CLK  
CLK  
OUT  
OUT  
f
REFERENCE  
Internal Reference Voltage, REF  
Internal Reference Voltage Drift  
(Notes 4, 5)  
(Note 3)  
1.0  
-
1.25  
0.34  
-
1.3  
-
V
OUT  
o
mV/ C  
Reference Input Voltage Range, V  
(Note 3)  
0.5  
2.0  
V
REF  
10-1718  
HI5780  
Electrical Specifications AV , DV = 5.00V, V  
= 2.0V, f  
= 80 MSPS, R  
= 200Ω, R  
= 3.3k,  
REF  
DD  
DD  
REF  
CLK  
LOAD  
o
T = 25 C (Continued)  
A
HI5780JCQ  
TYP  
PARAMETER  
DIGITAL INPUTS (D9-D0, CLK, BLK, PD)  
Input Logic High Voltage, V  
TEST CONDITIONS  
MIN  
MAX  
UNITS  
(Note 5)  
(Note 5)  
(Note 5)  
(Note 5)  
(Note 3)  
2.15  
-
-
V
IH  
Input Logic Low Voltage, V  
-
-
-
-
0.85  
V
IL  
Input Logic Current, I  
Input Logic Current, I  
5
-
µA  
µA  
pF  
IH  
IL  
-5  
-
-
Digital Input Capacitance, C  
3.0  
-
IN  
TIMING CHARACTERISTICS  
Data Setup Time, t  
(See Figure 1, Note 3)  
(See Figure 1, Note 3)  
(See Figure 1, Note 3)  
(See Figure 1, Note 3)  
5.0  
1.0  
-
3.0  
0
-
-
-
-
ns  
ns  
ns  
ns  
SU  
Data Hold Time, t  
HLD  
Propagation Delay Time, t  
8.0  
-
PD  
CLK Pulse Width, t  
, t  
6.25  
PW1 PW2  
POWER SUPPLY CHARACTERISTICS  
IV  
(Notes 4, 5)  
(Note 5)  
-
-
-
20  
30  
150  
-
mA  
mW  
mW  
DD  
Power Dissipation  
Sleep Mode Power Consumption  
NOTES:  
100  
1.25  
PD = 1 (Note 4)  
2. R  
is connected to I  
(pin 24) and R  
is connected to I  
(pin 17).  
REF  
LOAD  
OUT  
REF  
3. Parameter guaranteed by design or characterization and not production tested.  
o
4. Typical values are test results at T = 25 C.  
A
o
5. All devices are 100% tested at 25 C.  
Timing Diagrams  
50%  
CLK  
D9-D0  
1
GLITCH AREA = 1  
/2 (H x W)  
/
2 LSB ERROR BAND  
V
HEIGHT (H)  
IOUT  
tPD  
tSETT  
t(ps)  
WIDTH (W)  
FIGURE 1. FULL SCALE SETTLING TIME DIAGRAM  
FIGURE 2. PEAK GLITCH AREA (SINGLET) MEASUREMENT  
METHOD  
10-1719  
HI5780  
Timing Diagrams (Continued)  
tPW1  
tPW2  
50%  
CLK  
tSU  
tSU  
tSU  
tHLD  
tHLD  
tHLD  
D9-D0  
tSETT  
tPD  
1
/
2 LSB  
CHANGE  
IOUT  
1
/
2 LSB  
CHANGE  
tSETT  
tSETT  
tPD  
tPD  
FIGURE 3. PROPAGATION DELAY, SETUP TIME AND MINIMUM PULSE WIDTH DIAGRAM  
Pin Descriptions  
PIN  
PIN NAME  
DESCRIPTION  
1-7, 30-32  
D0 (LSB) thru Digital Data Bit 0, the least significant bit thru digital data Bit 9, the most significant bit.  
D9 (MSB)  
9
CLK  
DV  
Data Clock Pin 100kHz to 80MHz.  
Digital Logic Supply +5V.  
13, 28  
15, 27  
20, 21  
23  
DD  
DGND  
AV  
Digital Ground.  
Analog Supply +5V.  
DD  
BLK  
AGND  
PD  
Output Blanking pin. When set (‘1’) this pin zeros the I  
Analog Ground Supply Current Return pin.  
pin.  
OUT  
25  
11  
Power Down Mode pin. This pin when set (‘1’) places the HI5780 in lower power mode and zeros the  
output. Power consumption is reduced.  
24  
23  
18  
17  
19  
14  
22  
I
I
Current Output pin.  
OUT  
Complementary Current Output pin.  
OUT  
REF  
Bandgap Reference Voltage Output.  
OUT  
I
Reference Current setting resistor connected from here to Ground.  
Reference Voltage Input pin.  
REF  
V
REF  
VB  
VG  
Bias Voltage Generator Bypass Capacitor connected from here to Ground.  
Reference Amplifier Bypass Capacitor connected from here to AV  
.
DD  
10-1720  
HI5780  
Typical Performance Curves  
1.0  
0.75  
0.5  
2.0  
1.5  
1.0  
0.5  
0
0.25  
0
-0.5  
-1.0  
-1.5  
-2.0  
-0.25  
-0.5  
-0.75  
-1.0  
0
100 200 300 400 500 600 700 800 900 1000  
0
100 200 300 400 500 600 700 800 900 1000  
CODE  
CODE  
FIGURE 4. DIFFERENTIAL LINEARITY  
FIGURE 5. INTEGRAL LINEARITY (BEST FIT - STRAIGHT LINE)  
ATTEN 10dB  
L -10.0dBm  
MKR -48.50dB  
23  
22  
21  
20  
19  
18  
17  
16  
15  
R
10dB/  
2.00MHz  
-10  
-20  
-30  
HI5780  
fS = 40 MSPS  
fO = 2MHz  
-40  
S
-50  
-60  
-70  
-80  
-90  
-100  
START 0Hz  
RBW 1.0kHz  
STOP 20.00MHz  
SWP 50.0s  
10  
20  
30  
40  
50  
60  
MHz  
70  
80  
90  
100  
VBW 1.0kHz  
FIGURE 6. POWER SUPPLY CURRENT vs CLOCK FREQUENCY  
FIGURE 7. SPURIOUS FREE DYNAMIC RANGE TO NYQUIST  
ATTEN 10dB  
MKR -75.00dB  
RL -10.0dBm  
10dB/  
33kHz  
HI5780  
fS = 40 MSPS  
fO = 2MHz  
S
CENTER 2.000MHz  
RBW 300Hz  
SPAN 2.000MHz  
SWP 56.0s  
VBW 300Hz  
FIGURE 8. SPURIOUS FREE DYNAMIC RANGE WITHIN A WINDOW  
10-1721  
HI5780  
Reference  
Detailed Description  
The internal reference in the HI5780 is a 1.25V (typical)  
bandgap voltage reference. The internal reference is buff-  
ered by an amplifier to provide adequate drive for the current  
cells. Reference Out (REFOUT) is connected to the VREF pin.  
The Full Scale Output Current is controlled by the resistor  
connected to IREF. The full scale output voltage, is set by the  
following equation:  
The HI5780 is a 10-bit, current out D/A converter. The DAC  
can convert at 80 MSPS and runs on +5V supplies. The  
HI5780 achieves its low power and high speed performance  
from an advanced CMOS process. The HI5780 consumes  
150mW (Maximum) and has a power down mode that only  
consumes 1.25mW when in sleep mode. The HI5780 is an  
excellent converter to be used for communications applica-  
tions and high performance video systems.  
V
(Full Scale) = V  
x 16(R  
/R  
).  
OUT  
REF  
LOAD REF  
Digital Inputs  
Applications  
The HI5780 is a TTL/CMOS-compatible D/A. Data is latched  
by a 10-bit latch. Once latched data inputs D0 (LSB) thru D9  
(MSB) are decoded to the internal current cells; the internal  
latch and switching current source controls are implemented  
in CMOS technology to maintain high switching speeds and  
low power consumption.  
Voltage Conversion of the Output  
To convert the output current of the D/A converter to a  
voltage, an amplifier should be used as shown in Figure 5.  
The DAC needs a 50termination resistor on the IOUT pin to  
ensure proper settling. The HFA1110 has an internal feed-  
back resistor to compensate for high frequency operation.  
Clocks and Termination  
The internal 10-bit register is updated on the rising edge of  
the clock. Since the HI5780 clock rate can run to 80MHz, to  
minimize reflections and clock noise into the part, proper ter-  
mination should be used. In PCB layout clock runs should be  
kept short and have a minimum of loads. To guarantee con-  
sistent results from board to board, controlled impedance  
PCBs should be used with a characteristic line impedance,  
ZO, of 50.  
+5V  
2
1
HFA1110  
HI5780  
DAC  
8
-
+
21  
4
IOUT  
50Ω  
50Ω  
To terminate the clock line a shunt terminator to ground is the  
most effective type at a 80 MSPS clock rate. A typical value  
for termination can be determined by the equation:  
6
5
-5.2V  
FIGURE 10. HIGH SPEED CURRENT TO VOLTAGE CONVERSION  
R
= Z ,  
O
T
for the termination resistor. For a controlled impedance  
board with a ZO of 50, the RT = 50. Shunt termination is  
best used at the receiving end of the transmission line or as  
close to the HI5780 CLK pin as possible.  
Definition of Specifications  
Integral Linearity Error, INL, is the measure of the worst  
case point that deviates from a best fit straight line of data  
values along the transfer curve.  
Differential Linearity Error, DNL, is the measure of the  
step size output deviation from code to code. Ideally the step  
size should be 1 LSB. A DNL specification of 1 LSB or less  
guarantees monotonicity.  
HI5780  
DAC  
ZO = 50Ω  
CLK  
RT = 50Ω  
Output Voltage Full Scale Settling Time, is the time  
required from the 50% point on the clock input for a full scale  
step to settle within an 1/2 LSB error band.  
FIGURE 9. AC TERMINATION OF THE HI5780 CLOCK LINE  
Glitch Area, GE, is the switching transient appearing on the  
output during a code transition. It is measured as the area  
under the curve and expressed as a Volt-Time specification.  
Rise and Fall times and propagation delay of the line will be  
affected by the Shunt Terminator. The terminator can be  
connected to DGND.  
Differential Gain, AV, is the gain error from an ideal sine  
wave with a normalized amplitude.  
Noise Reduction  
Differential Phase, Φ, is the phase error from and ideal  
sine wave.  
To reduce power supply noise, separate analog and digital  
power supplies should be used with 0.1µF and 0.01µF  
ceramic capacitors placed as close to the body of the  
Spurious Free Dynamic Range, SFDR, is the amplitude  
difference from a fundamental to the largest harmonically or  
non-harmonically related spur. A sine wave is loaded into the  
D/A and the output filtered at 1/2 the clock frequency to elim-  
inate noise from clocking alias terms.  
HI5780 as possible on the analog (AVDD) and digital (DVDD  
)
supplies. The analog and digital ground returns should be  
connected together back at the device to ensure proper  
operation on power up.  
10-1722  
HI5780  
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.  
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without  
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate  
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which  
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com  
Sales Office Headquarters  
NORTH AMERICA  
EUROPE  
ASIA  
Intersil Corporation  
Intersil SA  
Mercure Center  
100, Rue de la Fusee  
1130 Brussels, Belgium  
TEL: (32) 2.724.2111  
FAX: (32) 2.724.22.05  
Intersil (Taiwan) Ltd.  
Taiwan Limited  
7F-6, No. 101 Fu Hsing North Road  
Taipei, Taiwan  
Republic of China  
TEL: (886) 2 2716 9310  
FAX: (886) 2 2715 3029  
P. O. Box 883, Mail Stop 53-204  
Melbourne, FL 32902  
TEL: (407) 724-7000  
FAX: (407) 724-7240  
Spec Number  
10-1723  
配单直通车
HI5780JCQ产品参数
型号:HI5780JCQ
是否Rohs认证: 不符合
生命周期:Obsolete
包装说明:PLASTIC, MQFP-32
Reach Compliance Code:not_compliant
风险等级:5.85
转换器类型:D/A CONVERTER
输入位码:BINARY
输入格式:PARALLEL, WORD
JESD-30 代码:S-PQFP-G32
JESD-609代码:e0
最大线性误差 (EL):0.1953%
位数:10
功能数量:1
端子数量:32
最高工作温度:75 °C
最低工作温度:-20 °C
封装主体材料:PLASTIC/EPOXY
封装代码:QFP
封装等效代码:QFP32,.35SQ,32
封装形状:SQUARE
封装形式:FLATPACK
电源:5 V
认证状态:Not Qualified
标称安定时间 (tstl):0.006 µs
子类别:Other Converters
最大压摆率:30 mA
标称供电电压:5 V
表面贴装:YES
技术:CMOS
温度等级:COMMERCIAL EXTENDED
端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING
端子节距:0.8 mm
端子位置:QUAD
Base Number Matches:1
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