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  • HI5860IBZ图
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  • HI5860IBZ
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产品型号HI5860IBZ的概述

芯片 HI5860IBZ 概述 HI5860IBZ是一款高性能的集成电路,属于电源管理IC(PMIC)系列。该芯片设计用于多种应用领域,包括但不限于移动设备、智能家居、物联网设备等,致力于提供高效的电源管理解决方案。凭借其低功耗、高效率和灵活的输出特性,HI5860IBZ在现代电子设备中扮演着关键的角色。 芯片 HI5860IBZ 的详细参数 HI5860IBZ 具有多项重要参数,使其在电源管理领域中具备竞争力。其关键技术参数包括: 1. 输入电压范围:该芯片支持广泛的输入电压,通常在 3V 到 20V 之间。这使得它能够兼容不同类型的电源。 2. 输出电压:HI5860IBZ 能够提供多种输出电压选项,其可调范围一般在 1.2V 至 5V 之间。 3. 输出电流:芯片的输出电流能力达到 1A,适合为各种负载供电。 4. 转换效率:该芯片的效率可高达 90% 以上,这对于电池供电设备尤...

产品型号HI5860IBZ的Datasheet PDF文件预览

HI5860  
®
Data Sheet  
May 4, 2005  
FN4654.6  
12-Bit, 130MSPS, High Speed D/A  
Converter  
The HI5860 is a 12-bit, 130MSPS (Mega Samples Per  
Second), high speed, low power, D/A converter which is  
implemented in an advanced CMOS process. Operating  
from a single +3V to +5V supply, the converter provides  
20mA of full scale output current and includes  
edge-triggered CMOS input data latches. Low glitch energy  
and excellent frequency domain performance are achieved  
using a segmented current source architecture.  
Features  
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . .130MSPS  
• Low Power . . . 175mW at 5V, 32mW at 3V (At 100MSPS)  
• Integral Linearity Error (Typ) . . . . . . . . . . . . . . . ±0.5 LSB  
• Adjustable Full Scale Output Current. . . . . 2mA to 20mA  
• Internal 1.2V Bandgap Voltage Reference  
• Single Power Supply from +5V to +3V  
• Power Down Mode  
This device complements the HI5x60 and HI5x28 family of high  
speed converters, which includes 8, 10, 12, and 14-bit devices.  
• CMOS Compatible Inputs  
• Excellent Spurious Free Dynamic Range  
(76dBc, f = 50MSPS, f  
= 2.51MHz)  
Ordering Information  
S
OUT  
• Excellent Multitone Intermodulation Distortion  
• Pb-Free Available (RoHS Compliant)  
TEMP.  
PART  
RANGE  
(°C)  
PKG.  
CLOCK  
NUMBER  
PACKAGE  
DWG. # SPEED  
HI5860IA*  
-40 to 85 28 Ld TSSOP M28.173 130MHz  
Applications  
HI5860IB  
-40 to 85 28 Ld SOIC M28.3  
130MHz  
130MHz  
• Basestations (Cellular, WLL)  
• Medical/Test Instrumentation  
• Wireless Communications Systems  
• Direct Digital Frequency Synthesis  
• Signal Reconstruction  
HI5860IBZ  
(See Note)  
-40 to 85 28 Ld SOIC M28.3  
(PB-free)  
HI5860SOICEVAL1  
25  
Evaluation Platform  
130MHz  
*Add “-T” for tape and reel.  
NOTE: Intersil Pb-free products employ special Pb-free material  
sets; molding compounds/die attach materials and 100% matte tin  
plate termination finish, which are RoHS compliant and compatible  
with both SnPb and Pb-free soldering operations. Intersil Pb-free  
products are MSL classified at Pb-free peak reflow temperatures that  
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.  
• High Resolution Imaging Systems  
• Arbitrary Waveform Generators  
Pinout  
HI5860  
(SOIC, TSSOP)  
TOP VIEW  
D11 (MSB)  
1
2
3
4
5
6
7
8
9
28 CLK  
27 DV  
D10  
D9  
D8  
D7  
D6  
D5  
D4  
D3  
DD  
26 DCOM  
25 ACOM  
24 AV  
DD  
23 COMP2  
22 IOUTA  
21 IOUTB  
20  
ACOM  
D2 10  
D1 11  
19 COMP1  
18 FSADJ  
17 REFIO  
16 REFLO  
15 SLEEP  
D0 (LSB) 12  
NC 13  
NC 14  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
Copyright Intersil Americas Inc. 2000, 2005. All Rights Reserved  
1
All other trademarks mentioned are the property of their respective owners.  
HI5860  
Typical Applications Circuit  
HI5860  
(25) ACOM  
NC (13, 14)  
(15) SLEEP  
(16) REFLO  
D11  
D10  
D9  
D8  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
D11 (1)  
D10 (2)  
D9 (3)  
D8 (4)  
D7 (5)  
D6 (6)  
D5 (7)  
D4 (8)  
D3 (9)  
D2 (10)  
D1 (11)  
DCOM  
ACOM  
(17) REFIO  
0.1µF  
(18) FSADJ  
(22) IOUTA  
1.91kΩ  
R
SET  
D/A OUT  
50Ω  
50Ω  
(21) IOUTB  
(23) COMP2  
D/A OUT  
D0 (LSB) (12)  
CLK (28)  
50Ω  
(19) COMP1  
(20) ACOM  
0.1µF  
DCOM (26)  
FERRITE  
BEAD  
0.1µF  
BEAD  
DV  
(27)  
+5V OR +3V (V  
DD  
)
(24) AV  
DD  
DD  
+
+
10µH  
10µH  
10µF  
10µF  
0.1µF  
0.1µF  
Functional Block Diagram  
IOUTA IOUTB  
(LSB) D0  
D1  
D2  
CASCODE  
CURRENT  
SOURCE  
D3  
D4  
D5  
7 LSBs  
+
38  
38  
LATCH  
SWITCH  
MATRIX  
LATCH  
D6  
31 MSB  
SEGMENTS  
D7  
D8  
UPPER  
5-BIT  
DECODER  
31  
D9  
D10  
COMP2  
COMP1  
(MSB) D11  
CLK  
INT/EXT  
VOLTAGE  
REFERENCE  
BIAS  
GENERATION  
INT/EXT  
SELECT  
REFERENCE  
REFLO  
AV  
DD  
ACOM DV  
DCOM  
FSADJ  
SLEEP  
REFIO  
DD  
FN4654.6  
May 4, 2005  
2
HI5860  
Pin Descriptions  
PIN NO.  
PIN NAME  
PIN DESCRIPTION  
1-12  
D11 (MSB) Through Digital Data Bit 11, (Most Significant Bit) through Digital Data Bit 0, (Least Significant Bit).  
D0 (LSB)  
13,14  
15  
NC  
No Connect. (Available as 2 additional LSBs on the HI5960, 14 bit device).  
SLEEP  
Control Pin for Power-Down Mode. Sleep Mode is active high; connect to ground for Normal Mode. Sleep  
pin has internal 20µA active pulldown current.  
16  
17  
18  
REFLO  
REFIO  
FSADJ  
Connect to analog ground to enable internal 1.2V reference or connect to AV  
reference.  
to disable internal  
DD  
Reference voltage input if internal reference is disabled. Reference voltage output if internal reference is  
enabled. Use 0.1µF cap to ground when internal reference is enabled.  
Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output  
Current = 32 x V  
/R .  
FSADJ SET  
19  
21  
COMP1  
IOUTB  
For use in reducing bandwidth/noise. Recommended: Connect 0.1µF to AV  
.
DD  
The complementary current output of the device. Full scale output current is achieved when all input bits  
are set to binary 0.  
22  
23  
IOUTA  
Current output of the device. Full scale output current is achieved when all input bits are set to binary 1.  
Connect 0.1µF capacitor to ACOM.  
COMP2  
24  
AV  
Analog Supply (+2.7V to +5.5V).  
DD  
20, 25  
26  
ACOM  
DCOM  
Connect to Analog Ground.  
Connect to Digital Ground.  
27  
DV  
Digital Supply (+2.7V to +5.5V).  
DD  
28  
CLK  
Clock Input. Input data to the DAC passes through the “master” latches when the clock is low and is  
latched into the “master” latches when the clock is high. Data presented to the “slave” latch passes  
through when the clock is logic high and is latched into the “slave” latches when the clock is logic low.  
Adequate setup time must be allowed for the MSBs to pass through the thermometer decoder before the  
clock goes high. This master-slave arrangement comprises an edge-triggered flip-flop, with the DAC  
being updated on the rising clock edge. For optimum spectral performance, it is recommended that the  
clock edge be skewed such that setup time is larger than the hold time.  
FN4654.6  
3
May 4, 2005  
HI5860  
Absolute Maximum Ratings  
Thermal Information  
Thermal Resistance (Typical, Note 1)  
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C  
Maximum Storage Temperature Range. . . . . . . . . . -65°C to 150°C  
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C  
(SOIC - Lead Tips Only)  
Digital Supply Voltage DV  
to DCOM . . . . . . . . . . . . . . . . . +5.5V  
θ
(°C/W)  
75  
DD  
Analog Supply Voltage AV  
JA  
to ACOM. . . . . . . . . . . . . . . . . . +5.5V  
DD  
Grounds, ACOM TO DCOM . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V  
100  
Digital Input Voltages (D11-D0, CLK, SLEEP). . . . . . . DV  
Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AV  
+ 0.3V  
+ 0.3V  
DD  
DD  
Analog Output Current (I  
) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA  
OUT  
Operating Conditions  
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C°C  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the  
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTE:  
1. θ is measured with the component mounted on an evaluation PC board in free air.  
JA  
Electrical Specifications AV = DV = +5V (except where otherwise noted), V  
= Internal 1.2V, IOUTFS = 20mA,  
DD  
DD  
REF  
T
= 25°C for All Typical Value  
A
T
= -40°C TO 85°C  
A
PARAMETER  
SYSTEM PERFORMANCE  
Resolution  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
12  
-2.0  
-1.0  
-0.025  
-
-
-
Bits  
LSB  
LSB  
Integral Linearity Error, INL  
Differential Linearity Error, DNL  
“Best Fit” Straight Line (Note 8)  
±0.5  
±0.5  
-
+2.0  
+1.0  
(Note 8)  
(Note 8)  
(Note 8)  
Offset Error, I  
+0.025 % FSR  
OS  
Offset Drift Coefficient  
0.1  
-
ppm  
FSR/°C°  
C
Full Scale Gain Error, FSE  
Full Scale Gain Drift  
With External Reference (Notes 2, 8)  
With Internal Reference (Notes 2, 8)  
With External Reference (Note 8)  
-10  
-10  
-
±2  
±1  
+10  
+10  
-
% FSR  
% FSR  
±50  
ppm  
FSR/°C  
With Internal Reference (Note 8)  
-
±100  
-
ppm  
FSR/°C  
Full Scale Output Current, I  
2
-
-
20  
mA  
V
FS  
Output Voltage Compliance Range  
(Note 3, 8)  
-0.3  
1.25  
DYNAMIC CHARACTERISTICS  
Maximum Clock Rate, f  
Output Settling Time, (t  
(Note 3)  
130  
-
-
-
-
-
-
-
-
-
MHz  
ns  
CLK  
)
±0.05% (±2 LSB) (Note 8)  
-
-
-
-
-
-
-
35  
5
SETT  
Singlet Glitch Area (Peak Glitch)  
Output Rise Time  
R
= 25(Note 8)  
pV•s  
ns  
L
Full Scale Step  
Full Scale Step  
2.5  
2.5  
10  
50  
30  
Output Fall Time  
ns  
Output Capacitance  
Output Noise  
pF  
IOUTFS = 20mA  
IOUTFS = 2mA  
pA/Hz  
pA/Hz  
AC CHARACTERISTICS  
+5V Power Supply  
Spurious Free Dynamic Range,  
SFDR Within a Window  
f
= 100MSPS, f  
= 100MSPS, f  
= 20.2MHz, 10MHz Span (Notes 4, 8)  
= 5.04MHz, 4MHz Span (Notes 4, 8)  
-
-
-
77  
95  
95  
-
-
-
dBc  
dBc  
dBc  
CLK  
OUT  
f
CLK  
OUT  
f
= 50MSPS, f = 5.02MHz, 2MHz Span (Notes 4, 8)  
OUT  
CLK  
FN4654.6  
4
May 4, 2005  
HI5860  
Electrical Specifications AV = DV = +5V (except where otherwise noted), V = Internal 1.2V, IOUTFS = 20mA,  
REF  
DD  
DD  
T
= 25°C for All Typical Value (Continued)  
A
T
= -40°C TO 85°C  
A
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
-71  
-75  
-76  
55  
66  
74  
-
MAX  
UNITS  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
+5V Power Supply  
Total Harmonic Distortion (THD) to  
Nyquist  
f
f
f
= 100MSPS, f  
OUT  
= 4.0MHz (Notes 4, 8)  
-
-
-
-
-
-
-
-
-
-
-
-
CLK  
CLK  
CLK  
= 50MSPS, f  
= 25MSPS, f  
= 2.0MHz (Notes 4, 8)  
= 1.0MHz (Notes 4, 8)  
= 40.4MHz (Notes 4, 8)  
= 10.1MHz (Notes 4, 8)  
OUT  
OUT  
-
+5V Power Supply  
f
= 130MSPS, f  
= 130MSPS, f  
= 130MSPS, f  
= 130MSPS, f  
= 100MSPS, f  
= 100MSPS, f  
= 100MSPS, f  
= 100MSPS, f  
= 100MSPS, f  
-
CLK  
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
Spurious Free Dynamic Range,  
f
-
CLK  
SFDR to Nyquist (f  
/2)  
CLK  
f
= 5.02MHz, T = 25°C (Notes 4, 8)  
= 5.02MHz, T = Min to Max (Notes 4, 8)  
= 40.4MHz (Notes 4, 8)  
68  
66  
-
CLK  
f
CLK  
f
54  
62  
74  
-
CLK  
f
= 20.2MHz (Notes 4, 8)  
-
CLK  
f
= 5.04MHz, T = 25°C (Notes 4, 8)  
= 5.04MHz, T = Min to Max (Notes 4, 8)  
= 2.51MHz (Notes 4, 8)  
68  
66  
-
CLK  
f
CLK  
f
75  
64  
74  
-
-
-
-
-
-
-
-
-
CLK  
f
= 50MSPS, f  
= 50MSPS, f  
= 50MSPS, f  
= 50MSPS, f  
= 50MSPS, f  
= 25MSPS, f  
= 20MSPS, f  
= 20.2MHz (Notes 4, 8)  
-
CLK  
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
f
= 5.02MHz, T = 25°C (Notes 4, 8)  
= 5.02MHz, T = Min to Max (Notes 4, 8)  
= 2.51MHz (Notes 4, 8)  
68  
66  
-
CLK  
f
CLK  
f
76  
78  
78  
76  
CLK  
f
= 1.00MHz (Notes 4, 8)  
-
CLK  
f
= 1.0MHz (Notes 4, 8)  
-
CLK  
+5V Power Supply  
Multitone Power Ratio  
f
= 2.0MHz to 2.99MHz, 8 Tones at 110kHz  
-
CLK  
Spacing (Notes 4, 8)  
f
= 100MSPS, f  
= 10MHz to 14.95MHz, 8 Tones at 530kHz  
-
76  
-
dBc  
CLK  
OUT  
Spacing (Notes 4, 8)  
+3V Power Supply  
f
= 100MSPS, f  
= 100MSPS, f  
= 20.2MHz, 30MHz Span (Notes 4, 8)  
= 5.04MHz, 8MHz Span (Notes 4, 8)  
-
-
-
-
-
-
73  
92  
-
-
-
-
-
-
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
CLK  
OUT  
Spurious Free Dynamic Range,  
SFDR Within a Window  
f
CLK  
OUT  
f
= 50MSPS, f  
OUT  
= 5.02MHz, 8MHz Span (Notes 4, 8)  
= 4.0MHz (Notes 4, 8)  
92  
CLK  
+3V Power Supply  
Total Harmonic Distortion (THD) to  
Nyquist  
f
f
f
= 100MSPS, f  
OUT  
-71  
-75  
-75  
CLK  
CLK  
CLK  
= 50MSPS, f  
= 25MSPS, f  
= 2.0MHz (Notes 4, 8)  
= 1.0MHz (Notes 4, 8)  
OUT  
OUT  
FN4654.6  
5
May 4, 2005  
HI5860  
Electrical Specifications AV = DV = +5V (except where otherwise noted), V = Internal 1.2V, IOUTFS = 20mA,  
REF  
DD  
DD  
T
= 25°C for All Typical Value (Continued)  
A
T
= -40°C TO 85°C  
A
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
47  
66  
73  
48  
58  
72  
76  
53  
73  
-
MAX  
UNITS  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
+3V Power Supply  
f
= 130MSPS, f  
= 130MSPS, f  
= 130MSPS, f  
= 100MSPS, f  
= 100MSPS, f  
= 100MSPS, f  
= 100MSPS, f  
= 40.4MHz (Notes 4, 8)  
= 10.1MHz (Notes 4, 8)  
= 5.02MHz (Notes 4, 8)  
= 40.4MHz (Notes 4, 8)  
= 20.2MHz (Notes 4, 8)  
= 5.04MHz (Notes 4, 8)  
= 2.51MHz (Notes 4, 8)  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CLK  
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
Spurious Free Dynamic Range,  
SFDR to Nyquist (f /2)  
f
CLK  
CLK  
f
-
CLK  
f
-
CLK  
f
-
CLK  
f
-
CLK  
f
-
CLK  
f
= 50MSPS, f  
= 50MSPS, f  
= 50MSPS, f  
= 50MSPS, f  
= 50MSPS, f  
= 25MSPS, f  
= 20MSPS, f  
= 20.2MHz (Notes 4, 8)  
-
CLK  
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
f
= 5.02MHz, T = 25°C (Notes 4, 8)  
= 5.02MHz, T = Min to Max (Notes 4, 8)  
= 2.51MHz (Notes 4, 8)  
68  
66  
-
CLK  
f
CLK  
f
76  
76  
76  
75  
CLK  
f
= 1.00MHz(Notes 4, 8)  
-
CLK  
f
= 1.0MHz (Notes 4, 8)  
-
CLK  
+3V Power Supply  
Multitone Power Ratio  
f
= 2.0MHz to 2.99MHz, 8 Tones at 110kHz  
-
CLK  
Spacing (Notes 4, 8)  
f
= 100MSPS, f  
= 10MHz to 14.95MHz, 8 Tones at 530kHz  
-
75  
-
dBc  
CLK  
OUT  
Spacing (Notes 4, 8)  
VOLTAGE REFERENCE  
Internal Reference Voltage, V  
Pin 18 Voltage with Internal Reference  
1.13  
1.2  
±60  
±50  
1.28  
V
FSADJ  
Internal Reference Voltage Drift  
-
-
-
-
ppm/°C  
µA  
Internal Reference Output Current  
Sink/Source Capability  
Reference Input Impedance  
-
-
1
-
-
MΩ  
Reference Input Multiplying Bandwidth (Note 8)  
1.4  
MHz  
DIGITAL INPUTS D11-D0, CLK  
Input Logic High Voltage with  
5V Supply, V  
(Note 3)  
(Note 3)  
(Note 3)  
(Note 3)  
3.5  
2.1  
-
5
3
0
0
-
V
V
V
V
IH  
Input Logic High Voltage with  
3V Supply, V  
-
IH  
Input Logic Low Voltage with  
5V Supply, V  
1.3  
0.9  
IL  
Input Logic Low Voltage with  
3V Supply, V  
-
IL  
Sleep Input Current, I  
-25  
-20  
-10  
-
-
-
+25  
+20  
+10  
-
µA  
µA  
µA  
pF  
IH  
IH  
IL  
Input Logic Current, I  
Input Logic Current, I  
-
Digital Input Capacitance, C  
5
IN  
TIMING CHARACTERISTICS  
Data Setup Time, t  
See Figure 4 (Note 3)  
See Figure 4 (Note 3)  
See Figure 4  
-
-
1.5  
1.2  
2.5  
-
-
-
-
-
ns  
ns  
ns  
ns  
SU  
Data Hold Time, t  
HLD  
Propagation Delay Time, t  
-
PD  
CLK Pulse Width, t  
, t  
PW1 PW2  
See Figure 4 (Note 3)  
4
FN4654.6  
6
May 4, 2005  
HI5860  
Electrical Specifications AV = DV = +5V (except where otherwise noted), V = Internal 1.2V, IOUTFS = 20mA,  
REF  
DD  
DD  
T
= 25°C for All Typical Value (Continued)  
A
T
= -40°C TO 85°C  
A
PARAMETER  
POWER SUPPLY CHARACTERISTICS  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
AV  
Power Supply  
Power Supply  
(Notes 9)  
2.7  
5.0  
5.0  
23  
5
5.5  
V
V
DD  
DV  
(Notes 9)  
2.7  
5.5  
DD  
Analog Supply Current (I  
AVDD  
)
5V or 3V, IOUTFS = 20mA  
5V or 3V, IOUTFS = 2mA  
5V (Note 5)  
-
-
mA  
-
-
mA  
Digital Supply Current (I  
)
-
7
-
mA  
DVDD  
5V (Note 6)  
-
12  
13  
2.4  
6
-
mA  
5V (Note 7)  
-
-
mA  
3V (Note 5)  
-
-
mA  
3V (Note 6)  
-
-
mA  
3V (Note 7)  
-
5
-
mA  
Supply Current (I  
) Sleep Mode  
5V or 3V, IOUTFS = Don’t Care  
5V, IOUTFS = 20mA (Note 5)  
5V, IOUTFS = 20mA (Note 6)  
5V, IOUTFS = 20mA (Note 7)  
5V, IOUTFS = 2mA (Note 6)  
3V, IOUTFS = 20mA (Note 5)  
3V, IOUTFS = 20mA (Note 6)  
3V, IOUTFS = 20mA (Note 7)  
3V, IOUTFS = 2mA (Note 6)  
Single Supply (Note 8)  
-
2.7  
150  
175  
180  
80  
76  
87  
84  
32  
-
-
mA  
AVDD  
Power Dissipation  
-
-
mW  
mW  
mW  
mW  
mW  
mW  
mW  
mW  
% FSR/V  
-
200  
-
-
-
-
-
-
100  
-
-
-
-
-
Power Supply Rejection  
NOTES:  
-0.2  
+0.2  
2. Gain Error measured as the error in the ratio between the full scale output current and the current through R  
ratio should be 32.  
(typically 625µA). Ideally the  
SET  
3. Parameter guaranteed by design or characterization and not production tested.  
4. Spectral measurements made with differential transformer coupled output and no external filtering.  
5. Measured with the clock at 50MSPS and the output frequency at 10MHz.  
6. Measured with the clock at 100MSPS and the output frequency at 40MHz.  
7. Measured with the clock at 130MSPS and the output frequency at 10MHz.  
8. See “Definition of Specifications”.  
9. It is recommended that the output current be reduced to 12mA or less to maintain optimum performance for operation below 3V. DV and AV  
DD  
DD  
do not have to be equal.  
FN4654.6  
7
May 4, 2005  
HI5860  
by using a sinusoidal waveform as the external reference  
with the digital inputs set to all 1s. The frequency is  
increased until the amplitude of the output waveform is  
0.707 (-3dB) of its original value.  
Definition of Specifications  
Differential Linearity Error, DNL, is the measure of the  
step size output deviation from code to code. Ideally the step  
size should be 1 LSB. A DNL specification of 1 LSB or less  
guarantees monotonicity.  
Singlet Glitch Area, is the switching transient appearing on  
the output during a code transition. It is measured as the  
area under the overshoot portion of the curve and is  
expressed as a Volt-Time specification. This is tested using  
a single code transition across a major current source.  
Full Scale Gain Drift, is measured by setting the data inputs  
to be all logic high (all 1s) and measuring the output voltage  
through a known resistance as the temperature is varied  
from T  
to T . It is defined as the maximum deviation  
MIN  
MAX  
from the value measured at room temperature to the value  
measured at either T or T . The units are ppm of FSR  
Spurious Free Dynamic Range, SFDR, is the amplitude  
difference from the fundamental signal to the largest  
harmonically or non-harmonically related spur within the  
specified frequency window.  
MIN  
(full scale range) per °C.  
MAX  
Full Scale Gain Error, is the error from an ideal ratio of 32  
between the output current and the full scale adjust current  
Total Harmonic Distortion, THD, is the ratio of the RMS  
value of the fundamental output signal to the RMS sum of  
the first five harmonic components.  
(through R  
).  
SET  
Integral Linearity Error, INL, is the measure of the worst  
case point that deviates from a best fit straight line of data  
values along the transfer curve.  
Detailed Description  
The HI5860 is an 12-bit, current out, CMOS, digital to analog  
converter. Its maximum update rate is 130MSPS and can be  
powered by either single or dual power supplies in the  
recommended range of +3V to +5V. Operation with clock  
rates higher than 130MSPS is possible; please contact the  
factory for more information. It consumes less than 180mW  
of power when using a +5V supply with the data switching at  
130MSPS. The architecture is based on a segmented  
current source arrangement that reduces glitch by reducing  
the amount of current switching at any one time. In previous  
architectures that contained all binary weighted current  
sources or a binary weighted resistor ladder, the converter  
might have a substantially larger amount of current turning  
on and off at certain, worst-case transition points such as  
midscale and quarter scale transitions. By greatly reducing  
the amount of current switching at certain “major” transitions,  
the overall glitch of the converter is dramatically reduced,  
improving settling time, transient problems, and accuracy.  
Internal Reference Voltage Drift, is defined as the  
maximum deviation from the value measured at room  
temperature to the value measured at either T  
or T .  
MAX  
MIN  
The units are ppm per °C.  
Offset Drift, is measured by setting the data inputs to all  
logic low (all 0s) and measuring the output voltage through a  
known resistance as the temperature is varied from T to  
MIN  
. It is defined as the maximum deviation from the value  
T
MAX  
measured at room temperature to the value measured at  
either T or T . The units are ppm of FSR (full scale  
MIN  
MAX  
range) per degree °C.  
Offset Error, is measured by setting the data inputs to all  
logic low (all 0s) and measuring the output voltage through a  
known resistance. Offset error is defined as the maximum  
deviation of the output current from a value of 0mA.  
Output Settling Time, is the time required for the output  
voltage to settle to within a specified error band measured  
from the beginning of the output transition. The  
Digital Inputs and Termination  
The HI5860 digital inputs are guaranteed to CMOS levels.  
However, TTL compatibility can be achieved by lowering the  
supply voltage to 3V due to the digital threshold of the input  
buffer being approximately half of the supply voltage. The  
internal register is updated on the rising edge of the clock. To  
minimize reflections, proper termination should be  
implemented. If the lines driving the clock and the digital  
inputs are long 50lines, then 50termination resistors  
should be placed as close to the converter inputs as possible  
connected to the digital ground plane (if separate grounds  
are used). These termination resistors are not likely needed  
as long as the digital waveform source is within a few inches  
of the DAC.  
measurement is done by switching quarter scale.  
Termination impedance was 25due to the parallel  
resistance of the 50loading on the output and the  
oscilloscope’s 50input. This also aids the ability to resolve  
the specified error band without overdriving the oscilloscope.  
Output Voltage Compliance Range, is the voltage limit  
imposed on the output. The output impedance should be  
chosen such that the voltage developed does not violate the  
compliance range.  
Power Supply Rejection, is measured using a single power  
supply. The supply’s nominal +5V is varied ±10% and the  
change in the DAC full scale output is noted.  
Ground Planes  
Separate digital and analog ground planes should be used.  
All of the digital functions of the device and their  
Reference Input Multiplying Bandwidth, is defined as the  
3dB bandwidth of the voltage reference input. It is measured  
FN4654.6  
8
May 4, 2005  
HI5860  
corresponding components should be located over the  
digital ground plane and terminated to the digital ground  
plane. The same is true for the analog components and the  
analog ground plane. Consult Application Note 9853.  
Outputs  
IOUTA and IOUTB are complementary current outputs. The  
sum of the two currents is always equal to the full scale  
output current minus one LSB. If single ended use is  
desired, a load resistor can be used to convert the output  
current to a voltage. It is recommended that the unused  
output be either grounded or equally terminated. The voltage  
developed at the output must not violate the output voltage  
Noise Reduction  
To minimize power supply noise, 0.1µF capacitors should be  
placed as close as possible to the converter’s power supply  
pins, AV  
and DV . Also, the layout should be designed  
DD  
DD  
compliance range of -0.3V to 1.25V. R  
(the impedance  
LOAD  
using separate digital and analog ground planes and these  
capacitors should be terminated to the digital ground for  
loading each current output) should be chosen so that the  
desired output voltage is produced in conjunction with the  
output full scale current. If a known line impedance is to be  
driven, then the output load resistor should be chosen to  
match this impedance. The output voltage equation is:  
DV  
and to the analog ground for AV . Additional filtering  
DD  
DD  
of the power supplies on the board is recommended.  
Voltage Reference  
The internal voltage reference of the device has a nominal  
value of +1.2V with a ±60ppm/°C drift coefficient over the full  
temperature range of the converter. It is recommended that  
a 0.1µF capacitor be placed as close as possible to the  
REFIO pin, connected to the analog ground. The REFLO pin  
(16) selects the reference. The internal reference can be  
selected if pin 16 is tied low (ground). If an external  
reference is desired, then pin 16 should be tied high (the  
analog supply voltage) and the external reference driven into  
REFIO, pin 17. The full scale output current of the converter  
is a function of the voltage reference used and the value of  
V
= I  
X R .  
LOAD  
OUT  
OUT  
These outputs can be used in a differential-to-single-ended  
arrangement to achieve better harmonic rejection. The  
SFDR measurements in this data sheet were performed with  
a 1:1 transformer on the output of the DAC (see Figure 1).  
With the center tap grounded, the output swing of pins 21  
and 22 will be biased at zero volts. The loading as shown in  
Figure 1 will result in a 500mV signal at the output of the  
transformer if the full scale output current of the DAC is set  
to 20mA.  
R
. I should be within the 2mA to 20mA range,  
R
IS THE IMPEDANCE  
SET OUT  
EQ  
LOADING EACH OUTPUT  
though operation below 2mA is possible, with performance  
degradation.  
V
= (2 x I x R )V  
OUT EQ  
50Ω  
100Ω  
50Ω  
OUT  
IOUTB  
PIN 21  
If the internal reference is used, V  
will equal  
approximately 1.2V (pin 18). If an external reference is used,  
FSADJ  
50Ω  
PIN 22  
IOUTA  
HI5860  
V
will equal the external reference. The calculation for  
FSADJ  
I
(Full Scale) is:  
OUT  
I
(Full Scale) = (V  
/R X 32.  
50REPRESENTS THE  
OUT  
FSADJ SET)  
SPECTRUM ANALYZER  
If the full scale output current is set to 20mA by using the  
internal voltage reference (1.2V) and a 1.91kR  
resistor, then the input coding to output current will resemble  
the following:  
FIGURE 1.  
SET  
V
= 2 x I  
x R , where R is ~12.5. Allowing the  
EQ EQ  
OUT  
OUT  
center tap to float will result in identical transformer output,  
however the output pins of the DAC will have positive DC  
offset. Since the DAC’s output voltage compliance range is -  
0.3V to +1.25V, the center tap may need to be left floating or  
DC offset in order to increase the amount of signal swing  
available. The 50load on the output of the transformer  
represents the spectrum analyzer’s input impedance.  
TABLE 1. INPUT CODING vs OUTPUT CURRENT  
INPUT CODE (D11-D0)  
11 11111 11111  
IOUTA (mA)  
IOUTB (mA)  
20  
10  
0
0
10 00000 00000  
00 00000 00000  
10  
20  
FN4654.6  
9
May 4, 2005  
HI5860  
Timing Diagrams  
50%  
CLK  
1
GLITCH AREA =  
/ (H x W)  
2
V
D11-D0  
HEIGHT (H)  
ERROR BAND  
I
OUT  
t(ps)  
WIDTH (W)  
t
SETT  
t
PD  
FIGURE 2. OUTPUT SETTLING TIME DIAGRAM  
FIGURE 3. PEAK GLITCH AREA (SINGLET) MEASUREMENT  
METHOD  
t
t
PW2  
PW1  
50%  
CLK  
t
t
t
SU  
SU  
SU  
t
t
t
HLD  
HLD  
HLD  
D11-D0  
t
SETT  
t
PD  
I
OUT  
t
t
SETT  
SETT  
t
t
PD  
PD  
FIGURE 4. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM  
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.  
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality  
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without  
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and  
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result  
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see www.intersil.com  
FN4654.6  
10  
May 4, 2005  
配单直通车
HI5860IBZ产品参数
型号:HI5860IBZ
Brand Name:Intersil
生命周期:Unknown
IHS 制造商:INTERSIL CORP
零件包装代码:SOIC
包装说明:SOP, SOP28,.4
针数:28
Reach Compliance Code:compliant
Factory Lead Time:7 weeks
风险等级:5.63
Is Samacsys:N
最大模拟输出电压:1.25 V
最小模拟输出电压:-0.3 V
转换器类型:D/A CONVERTER
输入位码:BINARY
输入格式:PARALLEL, WORD
JESD-30 代码:R-PDSO-G28
JESD-609代码:e3
长度:17.9 mm
最大线性误差 (EL):0.0488%
湿度敏感等级:3
位数:12
功能数量:1
端子数量:28
最高工作温度:85 °C
最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY
封装代码:SOP
封装等效代码:SOP28,.4
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260
电源:3/5 V
认证状态:Not Qualified
座面最大高度:2.65 mm
标称安定时间 (tstl):0.035 µs
子类别:Other Converters
标称供电电压:5 V
表面贴装:YES
技术:CMOS
温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING
端子节距:1.27 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:30
宽度:7.5 mm
Base Number Matches:1
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