I0
I1
I2
I3
I4
1I
2I
1R
1I
2R
2I
1A
1R
1I
2A
2R
2I
1D
1A
1R
1I
2D
2A
2R
2I
1W
1D
1A
1R
1I
2W
2D
2A
2R
2I
1W
1D
1A
1R
2W
2D
2A
2R
1W
1D
1A
2W
2D
2A
1W
1D
2W
2D
1W
2W
one cycle
1I-1R: Instruction cache access
2I: Instruction virtual to physical address translation
2R: Register file read, Bypass calculation, Instruction decode, Branch address calculation
1A: Issue or slip decision, Branch decision
1A: Data virtual address calculation
1A-2A: Integer add, logical, shift
2A: Store Align
2A-2D: Data cache access and load align
1D: Data virtual to physical address translation
2W: Register file write
Figure 2 Pipeline
performs shifts and store alignment operations. Each of
these units is optimized to perform all operations in a single
processor cycle.
Integer Unit
The RM5271 implements the MIPS IV Instruction Set
Architecture, and is therefore fully upward compatible with
applications that run on processors implementing the ear-
lier generation MIPS I-III instruction sets. Additionally, the
RM5271 includes two implementation-specific instructions
not found in the baseline MIPS IV ISA but that are useful in
the embedded market place. These instructions are integer
multiply-accumulate (MAD) and 3-operand integer multiply
(MUL).
Integer Multiply/Divide
The RM5271 has a dedicated integer multiply/divide unit
optimized for high-speed multiply and multiply-accumulate
operations. Table 1 shows the performance of the multiply/
divide unit on each operation.
Table 1: Integer Multiply/Divide Operations
The RM5271 integer unit includes thirty-two general pur-
pose 64-bit registers, a load/store architecture with single
cycle ALU operations (add, sub, logical, shift) and an
autonomous multiply/divide unit. Additional register
resources include: the HI/LO result registers for the two-
operand integer multiply/divide operations, and the pro-
gram counter (PC).
Repeat
Rate
Stall
Cycles
Operand
Size
Opcode
Latency
MULT/U,
MAD/U
16 bit
3
2
3
2
3
6
0
0
1
2
0
32 bit
16 bit
32 bit
any
4
3
4
7
MUL
DMULT,
DMULTU
Register File
DIV, DIVD
any
any
36
68
36
68
0
0
The RM5271 has thirty-two general purpose registers with
register location 0 (r0) hard wired to a zero value. These
registers are used for scalar integer operations and
address calculation. The register file has two read ports
and one write port and is fully bypassed to minimize opera-
tion latency in the pipeline.
DDIV,
DDIVU
The baseline MIPS IV ISA specifies that the results of a
multiply or divide operation be placed in the Hi and Lo reg-
isters. These values can then be transferred to the general
purpose register file using the Move-from-Hi and Move-
from-Lo (MFHI/MFLO) instructions.
ALU
The RM5271 ALU consists of an integer adder/subtractor, a
logic unit, and a shifter. The adder performs address calcu-
lations in addition to arithmetic operations. The logic unit
performs all logical and zero shift data moves. The shifter
In addition to the baseline MIPS IV integer multiply instruc-
tions, the RM5271 also implements the 3-operand multiply
instruction, MUL. This instruction specifies that the multiply
Quantum Effect Devices
www.qedinc.com
RM5271 Microprocessor, Document Rev. 1.3
3
ETC [ ETC ]
