MC74HC74ADR2全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

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产品型号MC74HC74ADR2的概述

芯片MC74HC74ADR2的概述 MC74HC74ADR2是一款广泛应用于数字电路设计中的双触发器（D触发器）芯片，属于74HC系列。它的设计基于高速CMOS（互补金属氧化物半导体）技术，提供了较高的工作频率和较低的功耗，因此特别适合需要高速数据处理且对能耗有严格控制的电子设备。MC74HC74ADR2可用于各种应用，从简单的计数器到复杂的数据存储和状态机电路，显示出其灵活多变的特征。芯片MC74HC74ADR2的详细参数 MC74HC74ADR2的技术参数如下： - 电源电压 (VCC): 2V 至 6V - 逻辑高电平 (VIH): 0.7 x VCC (具体值依据工作电压不同) - 逻辑低电平 (VIL): 0.3 x VCC (具体值依据工作电压不同) - 输出电流 (IOH/ IOL): ± 25mA（在5V供电时） - 工作温度范围: -40°C 至 +85°C - 时...

产品型号MC74HC74ADR2的Datasheet PDF文件预览

High–Performance Silicon–Gate CMOS

The MC74HC74A is identical in pinout to the LS74. The device

inputs are compatible with standard CMOS outputs; with pullup

resistors, they are compatible with LSTTL outputs.

This device consists of two D flip–flops with individual Set, Reset,

and Clock inputs. Information at a D–input is transferred to the

corresponding Q output on the next positive going edge of the clock

input. Both Q and Q outputs are available from each flip–flop. The Set

and Reset inputs are asynchronous.

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MARKING

DIAGRAMS

PDIP–14

N SUFFIX

CASE 646

MC74HC74AN

AWLYYWW

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2.0 to 6.0 V

SOIC–14

D SUFFIX

CASE 751A

HC74A

AWLYWW

• Low Input Current: 1.0 µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

74A

ALYW

TSSOP–14

DT SUFFIX

CASE 948G

• Chip Complexity: 128 FETs or 32 Equivalent Gates

LOGIC DIAGRAM

RESET 1

= Assembly Location

WL or L = Wafer Lot

YY or Y = Year

WW or W = Work Week

DATA 1

CLOCK 1

PIN ASSIGNMENT

SET 1

PIN 14 = V

PIN 7 = GND

RESET 1

DATA 1

13 RESET 2

RESET 2

CLOCK 1

SET 1

DATA 2

11 CLOCK 2

10 SET 2

CLOCK 2

SET 2

GND

FUNCTION TABLE

Inputs

Set Reset Clock Data

Outputs

ORDERING INFORMATION

Device

Package

PDIP–14

Shipping

MC74HC74AN

2000 / Box

55 / Rail

No Change

MC74HC74AD

SOIC–14

TSSOP–14

MC74HC74ADR2

MC74HC74ADT

MC74HC74ADTR2

2500 / Reel

96 / Rail

*Both outputs will remain high as long as Set and Reset are low, but the output

states are unpredictable if Set and Reset go high simultaneously.

2500 / Reel

Semiconductor Components Industries, LLC, 2000

Publication Order Number:

March, 2000 – Rev. 8

MC74HC74A/D

MC74HC74A

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high–impedance cir-

DC Supply Voltage (Referenced to GND)

DC Input Voltage (Referenced to GND)

DC Output Voltage (Referenced to GND)

DC Input Current, per Pin

– 0.5 to + 7.0

– 0.5 to V

+ 0.5

out

± 20

cuit. For proper operation, V and

DC Output Current, per Pin

± 25

± 50

out

should be constrained to the

out

DC Supply Current, V

and GND Pins

range GND (V or V

)

in out

Unused inputs must always be

tied to an appropriate logic voltage

Power Dissipation in Still Air,

Plastic DIP†

SOIC Package†

TSSOP Package†

750

500

450

level (e.g., either GND or V ).

Unused outputs must be left open.

Storage Temperature

– 65 to + 150

stg

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP, SOIC or TSSOP Package)

260

300

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C

SOIC Package: – 7 mW/ C from 65 to 125 C

TSSOP Package: – 6.1 mW/ C from 65 to 125 C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

2.0

Max

Unit

DC Supply Voltage (Referenced to GND)

DC Input Voltage, Output Voltage (Referenced to GND)

Operating Temperature, All Package Types

6.0

V , V

in out

– 55 + 125

t , t

r f

Input Rise and Fall Time

(Figures 1, 2, 3)

= 2.0 V

= 3.0 V

= 4.5 V

= 6.0 V

1000

600

500

400

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

– 55 to

Symbol

Parameter

Test Conditions

25 C

Unit

85 C

125 C

2.0

3.0

4.5

6.0

1.5

2.1

Minimum High–Level Input

Voltage

= 0.1 V or V

– 0.1 V

1.5

2.1

1.5

2.1

out

20 µA

out

3.15

4.2

3.15

4.2

3.15

4.2

2.0

3.0

4.5

6.0

0.5

0.9

Maximum Low–Level Input

Voltage

= 0.1 V or V

– 0.1 V

0.5

0.9

0.5

0.9

out

20 µA

out

1.35

1.8

1.35

1.8

1.35

1.8

Minimum High–Level Output

Voltage

= V or V

2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

20 µA

out

= V or V |I

2.4 mA

4.0 mA

5.2 mA

3.0

4.5

6.0

2.48

3.98

5.48

2.34

3.84

5.34

2.2

3.7

5.2

IH IL out

out

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MC74HC74A

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

– 55 to

25 C

Symbol

Parameter

Test Conditions

85 C

125 C

Unit

Maximum Low–Level Output

Voltage

= V or V

2.0

4.5

6.0

0.1

20 µA

out

= V or V |I

2.4 mA

4.0 mA

5.2 mA

3.0

4.5

6.0

0.26

0.33

0.4

IL out

out

Maximum Input Leakage

Current

= V

or GND

6.0

± 0.1

± 1.0

µA

Maximum Quiescent Supply

Current (per Package)

6.0

2.0

or GND

= 0 µA

out

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book

(DL129/D).

AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6.0 ns)

Guaranteed Limit

– 55 to

Symbol

Parameter

25 C

Unit

85 C

125 C

MHz

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 4)

2.0

3.0

4.5

6.0

4.8

4.0

8.0

max

Maximum Propagation Delay, Clock to Q or Q

(Figures 1 and 4)

2.0

3.0

4.5

6.0

100

125

150

120

PLH

PHL

Maximum Propagation Delay, Set or Reset to Q or Q

(Figures 2 and 4)

2.0

3.0

4.5

6.0

105

130

160

130

PLH

PHL

Maximum Output Transition Time, Any Output

(Figures 1 and 4)

2.0

3.0

4.5

6.0

110

TLH

THL

Maximum Input Capacitance

—

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON

Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, V

= 5.0 V

Power Dissipation Capacitance (Per Flip–Flop)*

* Used to determine the no–load dynamic power consumption: P = C

ON Semiconductor High–Speed CMOS Data Book (DL129/D).

f + I

. For load considerations, see Chapter 2 of the

PD CC

CC CC

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MC74HC74A

TIMING REQUIREMENTS (Input t = t = 6.0 ns)

Guaranteed Limit

– 55 to

Symbol

Parameter

25 C

Unit

85 C

125 C

Minimum Setup Time, Data to Clock

(Figure 3)

2.0

3.0

4.5

6.0

100

120

3.0

Minimum Hold Time, Clock to Data

(Figure 3)

2.0

3.0

4.5

6.0

3.0

Minimum Recovery Time, Set or Reset Inactive to Clock

(Figure 2)

2.0

3.0

4.5

6.0

8.0

rec

Minimum Pulse Width, Clock

(Figure 1)

2.0

3.0

4.5

6.0

Minimum Pulse Width, Set or Reset

(Figure 2)

2.0

3.0

4.5

6.0

t , t

r f

Maximum Input Rise and Fall Times

(Figures 1, 2, 3)

2.0

3.0

4.5

6.0

1000

800

500

400

1000

800

500

400

1000

800

500

400

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MC74HC74A

SWITCHING WAVEFORMS

50%

SET OR

RESET

90%

CLOCK

GND

50%

10%

GND

PHL

50%

Q OR Q

1/f

max

PHL

PLH

90%

50%

10%

Q OR Q

CLOCK

Q or Q

rec

TLH

THL

50%

Figure 1.

GND

Figure 2.

TEST POINT

OUTPUT

VALID

50%

DATA

GND

DEVICE

UNDER

TEST

C *

50%

CLOCK

GND

Figure 3.

*Includes all probe and jig capacitance

Figure 4.

EXPANDED LOGIC DIAGRAM

4, 10

SET

2, 12

5, 9

DATA

3, 11

CLOCK

6, 8

1, 13

RESET

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MC74HC74A

PACKAGE DIMENSIONS

PDIP–14

N SUFFIX

CASE 646–06

ISSUE L

NOTES:

1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE

POSITION AT SEATING PLANE AT MAXIMUM

MATERIAL CONDITION.

2. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

3. DIMENSION B DOES NOT INCLUDE MOLD

FLASH.

4. ROUNDED CORNERS OPTIONAL.

INCHES

DIM MIN MAX

0.770 18.16

MILLIMETERS

MIN

MAX

19.56

6.60

4.69

0.53

1.78

0.715

0.240

0.145

0.015

0.040

0.260

0.185

0.021

0.070

6.10

3.69

0.38

1.02

0.100 BSC

2.54 BSC

0.052

0.008

0.115

0.095

0.015

0.135

1.32

0.20

2.92

2.41

0.38

3.43

0.300 BSC

7.62 BSC

SEATING

PLANE

0.039

0.39

1.01

0.015

SOIC–14

D SUFFIX

CASE 751A–03

ISSUE F

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

–A–

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

–B–

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

P 7 PL

0.25 (0.010)

MILLIMETERS

DIM MIN MAX

INCHES

MIN MAX

R X 45

8.55

3.80

1.35

0.35

0.40

8.75 0.337 0.344

4.00 0.150 0.157

1.75 0.054 0.068

0.49 0.014 0.019

1.25 0.016 0.049

–T–

SEATING

PLANE

1.27 BSC

0.050 BSC

0.25 0.008 0.009

0.25 0.004 0.009

D 14 PL

0.19

0.10

0.25 (0.010)

T B

5.80

0.25

6.20 0.228 0.244

0.50 0.010 0.019

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MC74HC74A

PACKAGE DIMENSIONS

TSSOP–14

DT SUFFIX

CASE 948G–01

ISSUE O

NOTES:

14X K REF

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

0.10 (0.004)

T U

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,

PROTRUSIONS OR GATE BURRS. MOLD FLASH

OR GATE BURRS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION. INTERLEAD FLASH OR

PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.

0.15 (0.006) T U

0.25 (0.010)

2X L/2

–U–

5. DIMENSION K DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN

EXCESS OF THE K DIMENSION AT MAXIMUM

MATERIAL CONDITION.

PIN 1

IDENT.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

DETAIL E

7. DIMENSION A AND B ARE TO BE DETERMINED

AT DATUM PLANE –W–.

0.15 (0.006) T U

MILLIMETERS

DIM MIN MAX

INCHES

MIN MAX

–V–

4.90

4.30

–––

5.10 0.193 0.200

4.50 0.169 0.177

J J1

1.20

––– 0.047

0.05

0.50

0.15 0.002 0.006

0.75 0.020 0.030

SECTION N–N

0.65 BSC

0.026 BSC

0.60 0.020 0.024

0.20 0.004 0.008

0.16 0.004 0.006

0.30 0.007 0.012

0.25 0.007 0.010

0.50

0.09

0.19

–W–

6.40 BSC

0.252 BSC

0.10 (0.004)

SEATING

PLANE

–T–

DETAIL E

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MC74HC74A

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes

withoutfurthernoticetoanyproductsherein. SCILLCmakesnowarranty,representationorguaranteeregardingthesuitabilityofitsproductsforanyparticular

purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,

including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be

validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.

SCILLCproductsarenotdesigned, intended, orauthorizedforuseascomponentsinsystemsintendedforsurgicalimplantintothebody, orotherapplications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or

death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold

SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable

attorneyfees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim

alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATION

NORTH AMERICA Literature Fulfillment:

CENTRAL/SOUTH AMERICA:

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST)

Email: ONlit–spanish@hibbertco.com

Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada

Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada

Email: ONlit@hibbertco.com

ASIA/PACIFIC: LDC for ON Semiconductor – Asia Support

Phone: 303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time)

Toll Free from Hong Kong & Singapore:

Fax Response Line: 303–675–2167 or 800–344–3810 Toll Free USA/Canada

001–800–4422–3781

N. American Technical Support: 800–282–9855 Toll Free USA/Canada

Email: ONlit–asia@hibbertco.com

EUROPE: LDC for ON Semiconductor – European Support

German Phone: (+1) 303–308–7140 (M–F 1:00pm to 5:00pm Munich Time)

Email: ONlit–german@hibbertco.com

JAPAN: ON Semiconductor, Japan Customer Focus Center

4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–8549

Phone: 81–3–5740–2745

French Phone: (+1) 303–308–7141 (M–F 1:00pm to 5:00pm Toulouse Time)

Email: ONlit–french@hibbertco.com

English Phone: (+1) 303–308–7142 (M–F 12:00pm to 5:00pm UK Time)

Email: ONlit@hibbertco.com

Email: r14525@onsemi.com

ON Semiconductor Website: http://onsemi.com

EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781

For additional information, please contact your local

Sales Representative.

*Available from Germany, France, Italy, England, Ireland

MC74HC74A/D

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MC74HC74ADR2产品参数

型号:	MC74HC74ADR2
生命周期：	Transferred
零件包装代码：	SOIC
包装说明：	SOP, SOP14,.25
针数：	14
Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01
风险等级：	5.28
系列：	HC/UH
JESD-30 代码：	R-PDSO-G14
JESD-609代码：	e0
长度：	8.65 mm
负载电容（CL）：	50 pF
逻辑集成电路类型：	D FLIP-FLOP
最大频率@ Nom-Sup：	20000000 Hz
最大I（ol）：	0.004 A
位数：	1
功能数量：	2
端子数量：	14
最高工作温度：	125 °C
最低工作温度：	-55 °C
输出极性：	COMPLEMENTARY
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装等效代码：	SOP14,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
包装方法：	TAPE AND REEL
电源：	2/6 V
传播延迟（tpd）：	30 ns
认证状态：	Not Qualified
座面最大高度：	1.75 mm
子类别：	FF/Latches
最大供电电压 (Vsup)：	6 V
最小供电电压 (Vsup)：	2 V
标称供电电压 (Vsup)：	5 V
表面贴装：	YES
技术：	CMOS
温度等级：	MILITARY
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
触发器类型：	POSITIVE EDGE
宽度：	3.9 mm
最小 fmax：	20 MHz
Base Number Matches：	1

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产品型号MC74HC74ADR2的概述

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