ADSP-BF561SKBCZ-6A新批次到货！

ADSP-BF561SKBCZ-6A新批次到货！22+   303只可发发货15818661396叶小姐

ADSP-BF561SKBCZ-6A特点：

• 两个Blackfin内核，每个内核的性能均高达600 MHz/1200 MMAC（共2400 MMAC），适合要求苛刻的信号处理应用

• 328 KB大容量片上存储器，设定为每个内核的独立L1存储器系统以及一个共享L2存储器空间

• 可满足成像与消费类多媒体应用需求的高数据吞吐率

• 面向应用的外设提供到各种音/视频转换器及通用ADC/DAC的无缝连接

• 328 KB片上存储器，可以配置为：

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• 每个内核具有32KB的L1指令存储器（SRAM/高速缓存）

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• 每个内核具有64KB的L1数据存储器（SRAM/高速缓存）

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• 每个内核具有4KB的L1暂存器

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• 128 KB的低延迟共享L2存储器

• 32位存储器控制器提供与多组外部SDRAM、SRAM、Flash或ROM的无缝连接

• 两个并行外设接口单元，支持ITU-R 656视频数据格式

• 两个双通道、全双工同步串行端口，支持8个立体声I2S通道

• 两个16通道DMA控制器，支持一维和二维数据传输

• SPI兼容端口

• 支持IrDA?的UART

• 12个定时器/计数器，支持PWM、脉宽和事件计数模式

• 48个可编程标志/通用I/O

• 事件处理器

• 两个看门狗定时器

• PLL，具有1倍 -63倍倍频能力

• 256引脚迷你BGA封装、297引脚稀疏PBGA封装

Dual symmetric 600 MHz high performance Blackfin cores 328K bytes of on-chip memory (see Memory Architecture on Page 4) Each Blackfin core includes Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter RISC-like register and instruction model for ease of programming and compiler-friendly support Advanced debug, trace, and performance monitoring Wide range of operating voltages, (see Operating Conditions on Page 20) 256-ball CSP_BGA (2 sizes) and 297-ball PBGA package options PERIPHERALS Dual 12-channel DMA controllers (supporting 24 peripheral DMAs) 2 memory-to-memory DMAs VOLTA REGULA EXTERNAL PORT FLASH/SDRAM CONTROL 32 32 16 16 BOOT ROM PAB EAB DAB DAB PPI0 JTAG TEST EMULATION GPIO SPI SPORT0 TIMERS IMDMA SPORT1 CONTROLLER B CORE SYSTEM/BUS INTERFACE B DEB UART IrDA DMA CONTROLLER1 DMA CONTROLLER2 PPI1 IRQ CONTROL/ WATCHDOG TIMER L1 INSTRUCTION MEMORY L1 DATA MEMORY L1 INSTRUCTION MEMORY L1 DATA MEMORY L2 SRAM 128K BYTES ADSP-BF561 2 internal memory-to-memory DMAs and 1 internal memory DMA controller 12 general-purpose 32-bit timers/counters with PWM capability SPI-compatible port UART with support for IrDA Dual watchdog timers Dual 32-bit core timers 48 programmable flags (GPIO) On-chip phase-locked loop capable of 0.5× to 64× frequency multiplication 2 parallel input/output peripheral interface units supporting ITU-R 656 video and glueless interface to analog front end ADCs 2 dual channel, full duplex synchronous serial ports supporting eight stereo I2 S channels

ADSP-BF561SKBCZ-6A：Blackfin processors do not define a separate I/O space. All resources are mapped through the flat 32-bit address space. Onchip I/O devices have their control registers mapped into memory mapped registers (MMRs) at addresses near the top of the 4G byte address space. These are separated into two smaller blocks, one which contains the control MMRs for all core functions, and the other which contains the registers needed for setup and control of the on-chip peripherals outside of the core. The core MMRs are accessible only by the core and only in supervisor mode and appear as reserved space by on-chip peripherals. The system MMRs are accessible by the core in supervisor mode and can be mapped as either visible or reserved to other devices, depending on the system protection model desired.