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  • PCM1795DBR图
  • 深圳市芯球通科技有限公司

     该会员已使用本站8年以上
  • PCM1795DBR 现货库存
  • 数量3000 
  • 厂家TI/德州仪器 
  • 封装SSOP28 
  • 批号19+ 
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  • PCM1795DBR图
  • 深圳市恒达亿科技有限公司

     该会员已使用本站12年以上
  • PCM1795DBR 现货库存
  • 数量5000 
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  • 集好芯城

     该会员已使用本站13年以上
  • PCM1795DBR 现货库存
  • 数量22648 
  • 厂家TI(德州仪器) 
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  • 深圳市拓亿芯电子有限公司

     该会员已使用本站12年以上
  • PCM1795DBR 现货库存
  • 数量12000 
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  • 深圳市宏捷佳电子科技有限公司

     该会员已使用本站12年以上
  • PCM1795DBR 现货库存
  • 数量60030 
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  • 深圳市宗天技术开发有限公司

     该会员已使用本站10年以上
  • PCM1795DBR 现货库存
  • 数量8000 
  • 厂家Burr-Brown(TI) 
  • 封装 
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  • 深圳市能元时代电子有限公司

     该会员已使用本站10年以上
  • PCM1795DBR 现货库存
  • 数量92000 
  • 厂家TI/德州仪器 
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  • 深圳市华来深电子有限公司

     该会员已使用本站13年以上
  • PCM1795DBR 现货库存
  • 数量2000 
  • 厂家TI 
  • 封装SSOP28 
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  • PCM1795DB图
  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • PCM1795DB 现货库存
  • 数量50 
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  • PCM1795DBR图
  • 深圳市集创讯科技有限公司

     该会员已使用本站5年以上
  • PCM1795DBR 优势库存
  • 数量6560 
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  • PCM1795DBR图
  • 深圳市拓森弘电子有限公司

     该会员已使用本站1年以上
  • PCM1795DBR
  • 数量5300 
  • 厂家TI(德州仪器) 
  • 封装SSOP-28 
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  • PCM1795DB图
  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • PCM1795DB
  • 数量65000 
  • 厂家TIBB 
  • 封装SSOP 
  • 批号23+ 
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  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • PCM1795DB
  • 数量13880 
  • 厂家TI/德州仪器 
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  • PCM1795DB图
  • 深圳市旺能芯科技有限公司

     该会员已使用本站4年以上
  • PCM1795DB
  • 数量15000 
  • 厂家TI/德州仪器 
  • 封装SSOP28 
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  • PCM1795DB图
  • 深圳市芯鹏泰科技有限公司

     该会员已使用本站8年以上
  • PCM1795DB
  • 数量7536 
  • 厂家Texas Instruments 
  • 封装28-SSOP 
  • 批号23+ 
  • 数据采集ADC/DAC专用型
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  • PCM1795DB图
  • 深圳市硅诺电子科技有限公司

     该会员已使用本站8年以上
  • PCM1795DB
  • 数量60714 
  • 厂家TI 
  • 封装SSOP28 
  • 批号17+ 
  • 原厂指定分销商,有意请来电或QQ洽谈
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  • PCM1795DBR图
  • 深圳市恒益昌科技有限公司

     该会员已使用本站6年以上
  • PCM1795DBR
  • 数量5000 
  • 厂家TI 
  • 封装SSOP28 
  • 批号25+ 
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  • 深圳市和诚半导体有限公司

     该会员已使用本站11年以上
  • PCM1795DB
  • 数量5600 
  • 厂家TI 
  • 封装SSOP28 
  • 批号23+ 
  • 100%深圳原装现货库存
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  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • PCM1795DBR
  • 数量119 
  • 厂家TI/德州仪器 
  • 封装NA/ 
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  • 集好芯城

     该会员已使用本站13年以上
  • PCM1795DB
  • 数量24202 
  • 厂家TI 
  • 封装SSOP (DB) 
  • 批号最新批次 
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  • 深圳市欧立现代科技有限公司

     该会员已使用本站12年以上
  • PCM1795DB
  • 数量5321 
  • 厂家TI 
  • 封装SSOP28 
  • 批号24+ 
  • 全新原装现货,欢迎询购!
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  • 深圳市宏诺德电子科技有限公司

     该会员已使用本站8年以上
  • PCM1795DBR
  • 数量68000 
  • 厂家TI 
  • 封装SSOP28 
  • 批号22+ 
  • 全新进口原厂原装,优势现货库存,有需要联系电话:18818596997 QQ:84556259
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  • PCM1795DB图
  • 深圳市欧瑞芯科技有限公司

     该会员已使用本站11年以上
  • PCM1795DB
  • 数量9500 
  • 厂家TI(德州仪器) 
  • 封装28-SSOP(0.209,5.30mm 宽) 
  • 批号23+/24+ 
  • 绝对原装正品,可开13%专票,欢迎采购!!!
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  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • PCM1795DBR
  • 数量9048 
  • 厂家TI(德州仪器) 
  • 封装SSOP28 
  • 批号23+ 
  • 原厂可订货,技术支持,直接渠道。可签保供合同
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  • PCM1795DBR图
  • 深圳市恒佳微电子有限公司

     该会员已使用本站12年以上
  • PCM1795DBR
  • 数量
  • 厂家2028 
  • 封装SSOP28 
  • 批号 
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  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • PCM1795DBR
  • 数量12500 
  • 厂家TI/德州仪器 
  • 封装SSOP-28 
  • 批号2023+ 
  • 绝对原装正品全新深圳进口现货,优质渠道供应商!
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  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • PCM1795DBR
  • 数量63615 
  • 厂家TI 
  • 封装SSOP28 
  • 批号2023+ 
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  • 深圳市集创讯科技有限公司

     该会员已使用本站5年以上
  • PCM1795DBR
  • 数量7500 
  • 厂家TI/德州仪器 
  • 封装SSOP-28 
  • 批号24+ 
  • 原装进口正品现货,假一罚十价格优势
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  • PCM1795DB图
  • 深圳市正信鑫科技有限公司

     该会员已使用本站12年以上
  • PCM1795DB
  • 数量3189 
  • 厂家TI 
  • 封装原厂封装 
  • 批号22+ 
  • 原装正品★真实库存★价格优势★欢迎来电洽谈
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  • 深圳市美思瑞电子科技有限公司

     该会员已使用本站12年以上
  • PCM1795DBR
  • 数量12245 
  • 厂家TI/德州仪器 
  • 封装SSOP28 
  • 批号22+ 
  • 现货,原厂原装假一罚十!
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  • 深圳市惊羽科技有限公司

     该会员已使用本站11年以上
  • PCM1795DB
  • 数量6328 
  • 厂家TI-德州仪器 
  • 封装TSSOP-28 
  • 批号▉▉:2年内 
  • ▉▉¥54.7元一有问必回一有长期订货一备货HK仓库
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  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • PCM1795DBR
  • 数量13500 
  • 厂家TEXAS INSTRUMENTS 
  • 封装2000 
  • 批号2023+ 
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  • 深圳市英德州科技有限公司

     该会员已使用本站2年以上
  • PCM1795DBR
  • 数量45200 
  • 厂家TI(德州仪器) 
  • 封装SSOP-28 
  • 批号1年内 
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  • 深圳市驰天熠电子有限公司

     该会员已使用本站1年以上
  • PCM1795DB
  • 数量33560 
  • 厂家TI(德州仪器) 
  • 封装SSOP-28 
  • 批号23+ 
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  • 深圳市华兴微电子有限公司

     该会员已使用本站16年以上
  • PCM1795DB
  • 数量5000 
  • 厂家TI 
  • 封装N/A 
  • 批号23+ 
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  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
  • PCM1795DB
  • 数量3577 
  • 厂家TI 
  • 封装28-SSOP(0.209,5.30mm 宽) 
  • 批号2023+ 
  • 全新原厂原装产品、公司现货销售
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产品型号PCM1795DB的概述

PCM1795DB 芯片概述 PCM1795DB是一款由德州仪器(Texas Instruments)公司生产的高性能数字模拟转换器(DAC),属于其PCM系列产品。这款芯片专为音频应用设计,具有极高的音质和精度,广泛应用于高保真音频播放设备、音响系统和专业音频设备中。PCM1795DB采用了最新的技术,能够提供24位分辨率,并支持高达192kHz的采样频率,确保在音频转换过程中尽可能保持音质的完整性。 PCM1795DB的内置数字滤波器可为用户提供多种滤波选项,以适应不同的音频处理需求。该芯片还提供了优异的动态范围和失真性能,适合用于对音质要求极高的场合,如高保真音响设备和数字音乐播放器。 PCM1795DB 的详细参数 PCM1795DB的主要技术参数如下: - 分辨率: 24位 - 最高采样率: 192kHz - 动态范围: 132 dB (A-weighted) - 总谐波失真...

产品型号PCM1795DB的Datasheet PDF文件预览

PCM1795  
www.ti.com ........................................................................................................................................................................................................ SLES248MAY 2009  
32-Bit, 192-kHz Sampling, Advanced Segment,  
Stereo Audio Digital-to-Analog Converter  
1
FEATURES  
APPLICATIONS  
A/V Receivers  
SACD Players  
DVD Players  
HDTV Receivers  
Car Audio Systems  
Digital Multitrack Recorders  
Other Applications Requiring 32-Bit Audio  
234567  
32-Bit Resolution  
Analog Performance:  
Dynamic Range: 123 dB  
THD+N: 0.0005%  
Differential Current Output: 3.9 mAPP  
8× Oversampling Digital Filter:  
Stop Band Attenuation: –98 dB  
Passband Ripple: ±0.0002 dB  
DESCRIPTION  
Sampling Frequency: 10 kHz to 200 kHz  
The PCM1795 is a monolithic CMOS integrated  
circuit  
System Clock: 128, 192, 256, 384, 512, or  
768 fS With Autodetect  
that  
includes  
stereo  
digital-to-analog  
converters (DACs) and support circuitry in a small  
SSOP-28 package. The data converters use TI’s  
advanced segment DAC architecture to achieve  
excellent dynamic performance and improved  
tolerance to clock jitter. The PCM1795 provides  
balanced current outputs, allowing the user to  
optimize analog performance externally. The  
PCM1795 accepts pulse code modulation (PCM) and  
direct stream digital (DSD) audio data formats,  
providing an easy interface to audio digital signal  
processors (DSPs) and decoder chips. The PCM1795  
also interfaces with external digital filter devices such  
as the DF1704, DF1706, and the PMD200 from  
Pacific Microsonics™. Sampling rates up to 200 kHz  
are supported. A full set of user-programmable  
functions is accessible through an SPI or I2C serial  
control port that supports register write and readback  
functions. The PCM1795 also supports the  
time-division-multiplexed (TDM) command and audio  
(TDMCA) data format.  
Accepts 16-, 24-, and 32-Bit Audio Data  
PCM Data Formats: Standard, I2S™, and  
Left-Justified  
DSD Format Interface Available  
Interface Available for Optional External Digital  
Filter or DSP  
TDMCA or Serial Port (SPI™/I2C™)  
User-Programmable Mode Controls:  
Digital Attenuation: 0 dB to –120 dB,  
0.5-dB/Step  
Digital De-Emphasis  
Digital Filter Roll-Off: Sharp or Slow  
Soft Mute  
Zero Flag for Each Output  
Compatible With PCM1792A and PCM1796  
(Pins and Mode Controls)  
Dual Supply Operation:  
5-V Analog, 3.3-V Digital  
5-V Tolerant Digital Inputs  
Small SSOP-28 Package  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
3
4
5
6
7
System Two, Audio Precision are trademarks of Audio Precision, Inc.  
SPI is a trademark of Motorola.  
I2S, I2C are trademarks of NXP Semiconductors.  
Pacific Microsonics is a trademark of Pacific Microsonics, Inc.  
Super Audio CD is a trademark of Sony Corporation.  
All other trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2009, Texas Instruments Incorporated  
PCM1795  
SLES248MAY 2009........................................................................................................................................................................................................ www.ti.com  
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with  
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.  
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more  
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.  
ORDERING INFORMATION(1)  
SPECIFIED  
PACKAGE-  
LEAD  
PACKAGE  
DESIGNATOR  
TEMPERATURE  
RANGE  
PACKAGE  
MARKING  
ORDERING  
NUMBER  
TRANSPORT MEDIA,  
QUANTITY  
PRODUCT  
PCM1795DB  
Tube  
PCM1795  
SSOP-28  
DB  
–25°C to +85°C  
PCM1795  
PCM1795DBR  
Tape and Reel  
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI  
web site at www.ti.com.  
ABSOLUTE MAXIMUM RATINGS(1)  
Over operating free-air temperature range, unless otherwise noted.  
VALUE  
–0.3 to +6.5  
–0.3 to +4  
±0.1  
UNIT  
VCC1, VCC2L, VCC2R  
V
V
V
V
Supply voltage  
VDD  
Supply voltage differences  
Ground voltage differences  
VCC1, VCC2L, VCC2R  
AGND1, AGND2, AGND3L, AGND3R, DGND  
±0.1  
LRCK, DATA, BCK, SCK, MSEL, RST, MS(2), MDI, MC,  
–0.3 to +6.5  
V
MDO(2), ZEROL(2), ZEROR(2)  
Digital input voltage  
ZEROL(3), ZEROR(3), MDO(3), MS(3)  
–0.3 to (VDD + 0.3) < 4  
V
V
Analog input voltage  
–0.3 to (VCC + 0.3) < 6.5  
Input current (any pins except supplies)  
Ambient temperature under bias  
Storage temperature  
±10  
–40 to +125  
–55 to +150  
+150  
mA  
°C  
°C  
°C  
°C  
Junction temperature  
Package temperature (IR reflow, peak)  
+260  
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating  
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) Input mode or I2C mode.  
(3) Output mode except for I2C mode.  
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ELECTRICAL CHARACTERISTICS  
All specifications at TA = +25°C, VCC1 = VCC2L = VCC2R = 5 V, VDD = 3.3 V, fS = 48 kHz, system clock = 256 fS, and 32-bit  
data, unless otherwise noted.  
PCM1795 DB  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
RESOLUTION  
Resolution  
DATA FORMAT (PCM Mode)  
Audio data interface format  
32  
Bits  
Standard, I2S, left-justified  
16-, 24-, 32-bit selectable  
Audio data bit length  
Audio data format  
MSB first, twos complement  
10  
fS  
Sampling frequency  
System clock frequency  
200  
kHz  
fS  
128, 192, 256, 384, 512, 768  
DATA FORMAT (DSD Mode)  
Audio data interface format  
DSD (direct stream digital)  
Audio data bit length  
Sampling frequency  
System clock frequency  
1
Bit  
fS  
2.8224  
MHz  
MHz  
2.8224  
11.2986  
DIGITAL INPUT/OUTPUT  
TTL  
compatible  
Logic family  
VIH  
2
VDC  
VDC  
µA  
Input logic level  
VIL  
0.8  
10  
IIH  
VIN = VDD  
VIN = 0 V  
Input logic current  
IIL  
–10  
µA  
VOH  
IOH = –2 mA  
IOL = 2 mA  
2.4  
VDC  
VDC  
Output logic level  
VOL  
0.4  
DYNAMIC PERFORMANCE (PCM MODE)(1)(2)  
fS = 48 kHz  
fS = 96 kHz  
0.0005  
0.001  
0.0015  
123  
0.001  
%
THD+N at VOUT = 0 dB  
%
fS = 192 kHz  
%
EIAJ, A-weighted, fS = 48 kHz  
EIAJ, A-weighted, fS = 96 kHz  
EIAJ, A-weighted, fS = 192 kHz  
EIAJ, A-weighted, fS = 48 kHz  
EIAJ, A-weighted, fS = 96 kHz  
EIAJ, A-weighted, fS = 192 kHz  
fS = 48 kHz  
120  
120  
116  
dB  
dB  
dB  
dB  
dB  
dB  
dB  
dB  
dB  
dB  
Dynamic range  
123  
123  
123  
Signal-to-noise ratio  
Channel separation  
123  
123  
119  
fS = 96 kHz  
118  
fS = 192 kHz  
117  
Level linearity error  
(1) Filter condition:  
VOUT = –120 dB  
±1  
THD+N: 20-Hz high-pass filter (HPF), 20-kHz AES17 low-pass filter (LPF)  
Dynamic range: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted  
Signal-to-noise ratio: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted  
Channel separation: 20-Hz HPF, 20-kHz AES17 LPF  
Analog performance specifications are measured using the System Two™ Cascade audio measurement system by Audio Precision™ in  
the averaging mode.  
(2) Dynamic performance and dc accuracy are specified at the output of the post-amplifier as shown in Figure 52.  
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ELECTRICAL CHARACTERISTICS (continued)  
All specifications at TA = +25°C, VCC1 = VCC2L = VCC2R = 5 V, VDD = 3.3 V, fS = 48 kHz, system clock = 256 fS, and 32-bit  
data, unless otherwise noted.  
PCM1795 DB  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
DYNAMIC PERFORMANCE (MONO MODE)(3)(4)(5)  
fS = 48 kHz  
0.0005  
0.001  
0.0015  
126  
%
%
THD+N at VOUT = 0 dB  
Dynamic range  
fS = 96 kHz  
fS = 192 kHz  
%
EIAJ, A-weighted, fS = 48 kHz  
EIAJ, A-weighted, fS = 96 kHz  
EIAJ, A-weighted, fS = 192 kHz  
EIAJ, A-weighted, fS = 48 kHz  
EIAJ, A-weighted, fS = 96 kHz  
EIAJ, A-weighted, fS = 192 kHz  
dB  
dB  
dB  
dB  
dB  
dB  
126  
126  
126  
Signal-to-noise ratio  
126  
126  
DSD MODE DYNAMIC PERFORMANCE (44.1 kHz, 64 fS)(3)(6)  
THD+N at FS  
2 V rms  
0.0007  
122  
%
Dynamic range  
–60 dB, EIAJ, A-weighted  
EIAJ, A-weighted  
dB  
dB  
Signal-to-noise ratio  
122  
ANALOG OUTPUT  
Gain error  
–7  
–3  
–2  
±2  
±0.5  
±0.5  
4
7
3
2
% of FSR  
% of FSR  
% of FSR  
mAPP  
Gain mismatch, channel-to-channel  
Bipolar zero error  
Output current  
At BPZ  
Full-scale (0 dB)  
At BPZ  
Center current  
–3.5  
mA  
DIGITAL FILTER PERFORMANCE  
De-emphasis error  
±0.1  
dB  
FILTER CHARACTERISTICS–1: SHARP ROLL-OFF  
±0.0002 dB  
–3 dB  
0.454  
0.49  
fS  
fS  
Passband  
Stop band  
Passband ripple  
0.546  
–98  
fS  
±0.0002  
dB  
dB  
s
Stop-band attenuation  
Stop band = 0.546 fS  
Delay time  
38/fS  
FILTER CHARACTERISTICS–2: SLOW ROLL-OFF  
±0.001 dB  
–3 dB  
0.21  
fS  
fS  
Passband  
0.448  
Stop band  
0.79  
–80  
fS  
Passband ripple  
Stop-band attenuation  
Delay time  
±0.001  
dB  
dB  
s
Stop band = 0.732 fS  
38/fS  
(3) Filter condition:  
THD+N: 20-Hz high-pass filter (HPF), 20-kHz AES17 low-pass filter (LPF)  
Dynamic range: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted  
Signal-to-noise ratio: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted  
Channel separation: 20-Hz HPF, 20-kHz AES17 LPF  
Analog performance specifications are measured using the System Two™ Cascade audio measurement system by Audio Precision™ in  
the averaging mode.  
(4) Dynamic performance and dc accuracy are specified at the output of the post-amplifier as shown in Figure 52.  
(5) Dynamic performance and dc accuracy are specified at the output of the measurement circuit as shown in Figure 54.  
(6) Dynamic performance and dc accuracy are specified at the output of the post-amplifier as shown in Figure 53.  
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PCM1795  
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ELECTRICAL CHARACTERISTICS (continued)  
All specifications at TA = +25°C, VCC1 = VCC2L = VCC2R = 5 V, VDD = 3.3 V, fS = 48 kHz, system clock = 256 fS, and 32-bit  
data, unless otherwise noted.  
PCM1795 DB  
PARAMETER  
POWER-SUPPLY REQUIREMENTS  
VDD  
TEST CONDITIONS  
MIN  
3
TYP  
3.3  
5
MAX  
3.6  
5.25  
8
UNIT  
VDC  
VDC  
VCC  
1
Voltage range  
VCC2L  
VCC2R  
4.75  
fS = 48 kHz  
fS = 96 kHz  
fS = 192 kHz  
fS = 44.1 kHz  
fS = 96 kHz  
fS = 192 kHz  
fS = 48 kHz  
fS = 96 kHz  
fS = 192 kHz  
6
11  
mA  
mA  
mA  
mA  
mA  
mA  
mW  
mW  
mW  
IDD  
21  
Supply current(7)  
18  
23  
ICC  
19  
20  
110  
131  
166  
141  
Power dissipation(7)  
TEMPERATURE RANGE  
Operating temperature  
Thermal resistance  
–25  
+85  
°C  
θJA  
SSOP-28  
+100  
°C/W  
(7) Input is bipolar zero (BPZ) data.  
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FUNCTIONAL BLOCK DIAGRAM  
IOUTL-  
LRCK  
Current  
Segment  
DAC  
VOUTL  
BCK  
Audio  
Data Input  
I/F  
DATA  
IOUTL+  
I/V and Filter  
RST  
VCOM  
L
x8  
Advanced  
Segment  
DAC  
Oversampling  
Digital Filter  
and  
IREF  
Bias  
and VREF  
VCOM  
R
Modulator  
MDO  
MDI  
MC  
Function Control  
IOUTR-  
Function  
Control I/F  
MS  
Current  
Segment  
DAC  
VOUTR  
IOUTR+  
MSEL  
I/V and Filter  
System  
Clock  
Manager  
ZEROL  
ZEROR  
Zero  
Detect  
Power Supply  
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PIN CONFIGURATION  
DB PACKAGE  
SSOP-28  
(TOP VIEW)  
VCC2L  
27 AGND3L  
ZEROL  
ZEROR  
MSEL  
LRCK  
DATA  
BCK  
1
2
28  
IOUTL-  
IOUTL+  
AGND2  
3
26  
25  
24  
23  
22  
21  
20  
4
5
VCC1  
6
VCOM  
VCOM  
IREF  
L
SCL  
7
R
DGND  
VDD  
8
9
10  
19 AGND1  
MS  
IOUTR-  
MDI 11  
MC 12  
18  
17  
IOUTR+  
MDO 13  
16 AGND3R  
VCC2R  
15  
14  
RST  
Table 1. TERMINAL FUNCTIONS  
TERMINAL  
NAME  
AGND1  
AGND2  
AGND3L  
AGND3R  
BCK  
NO.  
19  
24  
27  
16  
6
I/O  
I
DESCRIPTION  
Analog ground (internal bias)  
Analog ground (internal bias)  
Analog ground (left channel DACFF)  
Analog ground (right channel DACFF)  
Bit clock input(1)  
DATA  
DGND  
IOUTL+  
IOUTL–  
IOUTR+  
IOUTR–  
IREF  
5
I
Serial audio data input(2)  
8
O
O
O
O
I
Digital ground  
25  
26  
17  
18  
20  
4
Left channel analog current output+  
Left channel analog current output–  
Right channel analog current output+  
Right channel analog current output–  
Output current reference bias pin  
Left and right clock (fS) input(2)  
Mode control clock input(2)  
LRCK  
MC  
12  
11  
13  
10  
3
I
MDI  
I
Mode control data input(2)  
MDO  
I/O  
I/OI  
I
Mode control readback data output(3)  
Mode control chip-select input(4); active low  
I2C/SPI select(2); active low SPI select  
Reset(2); active low  
MS  
MSEL  
RST  
14  
I
(1) Schmitt-trigger input, 5-V tolerant.  
(2) Schmitt-trigger input, 5-V tolerant.  
(3) Schmitt-trigger input and output. 5-V tolerant input. In I2C mode, this pin becomes an open-drain 3-state output; otherwise, this pin is a  
CMOS output.  
(4) Schmitt-trigger input and output. 5-V tolerant input and CMOS output.  
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Table 1. TERMINAL FUNCTIONS (continued)  
TERMINAL  
NAME  
NO.  
7
I/O  
I
DESCRIPTION  
SCK  
System clock input(2)  
VCC  
1
23  
28  
15  
22  
21  
9
I/O  
I/O  
Analog power supply, 5 V  
VCC2L  
VCC2R  
Analog power supply (left channel DACFF), 5 V  
Analog power supply (right channel DACFF), 5 V  
Left channel internal bias decoupling pin  
Right channel internal bias decoupling pin  
Digital power supply, 3.3 V  
Zero flag for left channel(4)  
Zero flag for right channel(4)  
VCOM  
VCOM  
VDD  
L
R
ZEROL  
ZEROR  
1
2
8
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TIMING CHARACTERISTICS  
Start  
Repeated Start  
Stop  
t(D-HD)  
t(SDA-F)  
t(P-SU)  
t(BUF)  
t(D-SU)  
t(SDA-R)  
SDA  
SCL  
t(SCL-R)  
t(RS-HD)  
t(SP)  
t(LOW)  
t(SCL-F)  
t(S-HD)  
t(HI)  
t(RS-SU)  
Figure 1. Timing Definition on the I2C Bus  
TIMING REQUIREMENTS  
PARAMETER  
CONDITIONS  
Standard  
MIN  
MAX  
UNIT  
kHz  
kHz  
µs  
µs  
µs  
µs  
µs  
ns  
µs  
ns  
µs  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
µs  
ns  
pF  
ns  
100  
400  
f(SCL)  
t(BUF)  
t(LOW)  
t(HI)  
SCL clock frequency  
Fast  
Standard  
4.7  
Bus free time between stop and start conditions  
Low period of the SCL clock  
High period of the SCL clock  
Setup time for (repeated) start condition  
Hold time for (repeated) start condition  
Data setup time  
Fast  
1.3  
Standard  
Fast  
4.7  
1.3  
Standard  
Fast  
4
600  
Standard  
Fast  
4.7  
t(RS-SU)  
600  
t(S-HD)  
Standard  
Fast  
4
t(RS-HD)  
600  
Standard  
Fast  
250  
t(D-SU)  
100  
Standard  
Fast  
0
900  
900  
t(D-HD)  
Data hold time  
0
Standard  
Fast  
20 + 0.1 CB  
20 + 0.1 CB  
20 + 0.1 CB  
20 + 0.1 CB  
20 + 0.1 CB  
20 + 0.1 CB  
20 + 0.1 CB  
20 + 0.1 CB  
20 + 0.1 CB  
20 + 0.1 CB  
4
1000  
300  
t(SCL-R)  
t(SCL-R1)  
t(SCL-F)  
t(SDA-R)  
t(SDA-F)  
t(P-SU)  
Rise time of SCL signal  
Standard  
Fast  
1000  
300  
Rise time of SCL signal after a repeated start condition  
and after an acknowledge bit  
Standard  
Fast  
1000  
300  
Fall time of SCL signal  
Rise time of SDA signal  
Fall time of SDA signal  
Setup time for stop condition  
Standard  
Fast  
1000  
300  
Standard  
Fast  
1000  
300  
Standard  
Fast  
600  
C(B)  
t(SP)  
Capacitive load for SDA and SCL line  
Pulse duration of suppressed spike  
400  
50  
Fast  
Noise margin at high level for each connected device  
(including hysteresis)  
VNH  
0.2 VDD  
V
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TYPICAL CHARACTERISTICS: DIGITAL FILTER  
Digital Filter Response  
AMPLITUDE vs FREQUENCY  
AMPLITUDE vs FREQUENCY  
0
-20  
0.0005  
0.0004  
0.0003  
0.0002  
0.0001  
0
Frequency Response  
Sharp Roll-Off  
Passband Ripple  
Sharp Roll-Off  
-40  
-60  
-80  
-0.0001  
-0.0002  
-0.0003  
-0.0004  
-0.0005  
-100  
-120  
-140  
-160  
0
1
2
3
4
0
0.1  
0.2  
0.3  
0.4  
0.5  
Frequency (´ fS)  
Frequency (´ fS)  
Figure 2.  
Figure 3.  
AMPLITUDE vs FREQUENCY  
AMPLITUDE vs FREQUENCY  
0
-20  
0
-2  
Frequency Response  
Slow Roll-Off  
-4  
-40  
-6  
-60  
-8  
-80  
-10  
-12  
-14  
-16  
-18  
-20  
-100  
-120  
-140  
-160  
Transition Characteristics  
Slow Roll-Off  
0
1
2
3
4
0
0.1  
0.2  
0.3  
0.4  
0.5  
0.6  
Frequency (´ fS)  
Frequency (´ fS)  
Figure 4.  
Figure 5.  
10  
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TYPICAL CHARACTERISTICS: DIGITAL FILTER  
De-Emphasis Filter  
DE-EMPHASIS LEVEL vs FREQUENCY  
DE-EMPHASIS ERROR vs FREQUENCY  
0
-1  
-2  
-3  
-4  
-5  
-6  
-7  
-8  
-9  
-10  
0.5  
0.4  
fS = 32 kHz  
fS = 32 kHz  
0.3  
0.2  
0.1  
0
-0.1  
-0.2  
-0.3  
-0.4  
-0.5  
0
0
0
2
4
6
8
10  
12  
14  
0
0
0
2
4
6
8
10  
12  
14  
Frequency (kHz)  
Frequency (kHz)  
Figure 6.  
Figure 7.  
DE-EMPHASIS LEVEL vs FREQUENCY  
DE-EMPHASIS ERROR vs FREQUENCY  
0
-1  
-2  
-3  
-4  
-5  
-6  
-7  
-8  
-9  
-10  
0.5  
0.4  
fS = 44.1 kHz  
fS = 44.1 kHz  
0.3  
0.2  
0.1  
0
-0.1  
-0.2  
-0.3  
-0.4  
-0.5  
2
4
6
8
10  
12  
14  
16  
18  
20  
2
4
6
8
10  
12  
14  
16  
18  
20  
Frequency (kHz)  
Frequency (kHz)  
Figure 8.  
Figure 9.  
DE-EMPHASIS LEVEL vs FREQUENCY  
DE-EMPHASIS ERROR vs FREQUENCY  
0
-1  
-2  
-3  
-4  
-5  
-6  
-7  
-8  
-9  
-10  
0.5  
0.4  
fS = 48 kHz  
fS = 48 kHz  
0.3  
0.2  
0.1  
0
-0.1  
-0.2  
-0.3  
-0.4  
-0.5  
2
4
6
8
10 12 14 16 18 20 22  
2
4
6
8
10 12 14 16 18 20 22  
Frequency (kHz)  
Frequency (kHz)  
Figure 10.  
Figure 11.  
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TYPICAL CHARACTERISTICS: ANALOG DYNAMIC PERFORMANCE  
Supply Voltage Characteristics  
PCM mode, TA = +25°C, and VDD = 3.3 V; measured with circuit shown in Figure 52, unless otherwise noted.  
THD+N vs SUPPLY VOLTAGE  
DYNAMIC RANGE vs SUPPLY VOLTAGE  
0.01  
126  
124  
122  
120  
118  
116  
fS = 192 kHz  
fS = 96 kHz  
fS = 192 kHz  
fS = 96 kHz  
fS = 48 kHz  
0.001  
fS = 48 kHz  
0.0001  
4.50  
4.75  
5.00  
5.25  
5.50  
4.50  
4.75  
5.00  
5.25  
5.50  
Supply Voltage (V)  
Supply Voltage (V)  
Figure 12.  
Figure 13.  
SNR vs SUPPLY VOLTAGE  
CHANNEL SEPARATION vs SUPPLY VOLTAGE  
126  
124  
122  
120  
118  
116  
122  
120  
118  
116  
114  
112  
fS = 96 kHz  
fS = 48 kHz  
fS = 96 kHz  
fS = 48 kHz  
fS = 192 kHz  
fS = 192 kHz  
4.50  
4.75  
5.00  
5.25  
5.50  
4.50  
4.75  
5.00  
5.25  
5.50  
Supply Voltage (V)  
Supply Voltage (V)  
Figure 14.  
Figure 15.  
12  
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TYPICAL CHARACTERISTICS: ANALOG DYNAMIC PERFORMANCE  
Temperature Characteristics  
PCM mode, VDD = 3.3 V, and VCC = 5 V; measured with circuit shown in Figure 52, unless otherwise noted.  
THD+N vs FREE-AIR TEMPERATURE  
DYNAMIC RANGE vs FREE-AIR TEMPERATURE  
0.01  
126  
124  
122  
120  
118  
116  
fS = 96 kHz  
fS = 192 kHz  
fS = 192 kHz  
fS = 48 kHz  
0.001  
fS = 48 kHz  
fS = 96 kHz  
0.0001  
-50  
-25  
0
25  
50  
75  
100  
-50  
-25  
0
25  
50  
75  
100  
Free-Air Temperature (°C)  
Free-Air Temperature (°C)  
Figure 16.  
Figure 17.  
SNR vs FREE-AIR TEMPERATURE  
CHANNEL SEPARATION vs FREE-AIR TEMPERATURE  
126  
124  
122  
120  
118  
116  
122  
120  
118  
116  
114  
112  
fS = 96 kHz  
fS = 96 kHz  
fS = 48 kHz  
fS = 192 kHz  
fS = 192 kHz  
fS = 48 kHz  
-50  
-25  
0
25  
50  
75  
100  
-50  
-25  
0
25  
50  
75  
100  
Free-Air Temperature (°C)  
Free-Air Temperature (°C)  
Figure 18.  
Figure 19.  
AMPLITUDE vs FREQUENCY  
(Measurement Circuit: Figure 52)  
AMPLITUDE vs FREQUENCY  
(Measurement Circuit: Figure 52)  
0
-20  
0
-60-dB Output Spectrum  
-60-dB Output Spectrum  
BW = 20 kHz  
PCM Mode  
fS = 48 kHz  
BW = 100 kHz  
PCM Mode  
fS = 96 kHz  
-20  
-40  
-40  
32768 Point 8 Average  
TA = +25°C  
32768 Point 8 Average  
TA = +25°C  
-60  
-60  
VDD = 3.3 V  
VCC = 5 V  
VDD = 3.3 V  
VCC = 5 V  
-80  
-80  
-100  
-120  
-140  
-160  
-100  
-120  
-140  
-160  
0
2
4
6
8
10  
12  
14  
16  
18  
20  
0
10  
20  
30  
40  
50  
60  
70  
80  
90 100  
Frequency (kHz)  
Frequency (kHz)  
Figure 20.  
Figure 21.  
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TYPICAL CHARACTERISTICS: ANALOG DYNAMIC PERFORMANCE (continued)  
PCM mode, VDD = 3.3 V, and VCC = 5 V; measured with circuit shown in Figure 52, unless otherwise noted.  
AMPLITUDE vs FREQUENCY  
(Measurement Circuit: Figure 52)  
AMPLITUDE vs FREQUENCY  
(Measurement Circuit: Figure 52)  
-120  
-124  
-128  
-132  
-136  
-140  
-144  
-148  
-152  
-156  
-160  
-120  
-124  
-128  
-132  
-136  
-140  
-144  
-148  
-152  
-156  
-160  
-144-dB Output Spectrum  
-150-dB Output Spectrum  
BW = 20 kHz  
PCM Mode  
fS = 48 kHz  
BW = 20 kHz  
PCM Mode  
fS = 48 kHz  
32768 Point 8 Average  
TA = +25°C  
32768 Point 8 Average  
TA = +25°C  
VDD = 3.3 V  
VCC = 5 V  
VDD = 3.3 V  
VCC = 5 V  
100  
1 k  
10 k  
100  
1 k  
10 k  
Frequency (Hz)  
Frequency (Hz)  
Figure 22.  
Figure 23.  
THD+N vs INPUT LEVEL  
(Measurement Circuit: Figure 52)  
AMPLITUDE vs FREQUENCY  
(Measurement Circuit: Figure 53)  
10  
0
-20  
PCM Mode  
-60-dB Output Spectrum  
fS = 48 kHz  
TA = +25°C  
VDD = 3.3 V  
VCC = 5 V  
DSD Mode (FIR-2)  
32768 Point 8 Average  
TA = +25°C  
1
0.1  
-40  
VDD = 3.3 V  
VCC = 5 V  
-60  
-80  
0.01  
-100  
-120  
-140  
-160  
0.001  
0.0001  
-90 -80 -70 -60 -50 -40 -30 -20 -10  
0
0
2
4
6
8
10  
12  
14  
16  
18  
20  
Input Level (dBFS)  
Frequency (kHz)  
Figure 24.  
Figure 25.  
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TYPICAL CHARACTERISTICS: ANALOG FIR FILTER PERFORMANCE IN DSD MODE  
All specifications at DBCK = 2.8224 MHz (44.1 kHz × 64 fS), and 50% modulation DSD data input, unless otherwise noted.  
GAIN vs FREQUENCY  
GAIN vs FREQUENCY(1)  
0
-1  
-2  
-3  
-4  
-5  
-6  
0
-10  
-20  
-30  
-40  
-50  
-60  
DSD Filter-1  
Low Bandwidth  
DSD Filter-1  
High Bandwidth  
fC = 185 kHz  
Gain = -6.6 dB  
0
0
0
50  
50  
50  
100  
150  
200  
0
0
0
500 k  
Frequency (Hz)  
1 M  
1.5 M  
Frequency (kHz)  
Figure 26.  
Figure 27.  
GAIN vs FREQUENCY  
GAIN vs FREQUENCY  
0
-1  
-2  
-3  
-4  
-5  
-6  
0
-10  
-20  
-30  
-40  
-50  
-60  
DSD Filter-2  
Low Bandwidth  
DSD Filter-2  
High Bandwidth  
fC = 90 kHz  
Gain = 0.3 dB  
100  
150  
200  
500 k  
Frequency (Hz)  
1 M  
1.5 M  
Frequency (kHz)  
Figure 28.  
Figure 29.  
GAIN vs FREQUENCY  
GAIN vs FREQUENCY  
0
-1  
-2  
-3  
-4  
-5  
-6  
0
-10  
-20  
-30  
-40  
-50  
-60  
DSD Filter-3  
Low Bandwidth  
DSD Filter-3  
High Bandwidth  
fC = 85 kHz  
Gain = -1.5 dB  
100  
150  
200  
500 k  
Frequency (Hz)  
1 M  
1.5 M  
Frequency (kHz)  
Figure 30.  
Figure 31.  
(1) This gain is in comparison to PCM 0 dB, when the DSD input signal efficiency is 50%.  
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TYPICAL CHARACTERISTICS: ANALOG FIR FILTER PERFORMANCE IN DSD MODE (continued)  
All specifications at DBCK = 2.8224 MHz (44.1 kHz × 64 fS), and 50% modulation DSD data input, unless otherwise noted.  
GAIN vs FREQUENCY  
GAIN vs FREQUENCY  
0
-1  
-2  
-3  
-4  
-5  
-6  
0
-10  
-20  
-30  
-40  
-50  
-60  
DSD Filter-4  
Low Bandwidth  
DSD Filter-4  
High Bandwidth  
fC = 94 kHz  
Gain = -3.3 dB  
0
50  
100  
150  
200  
0
500 k  
Frequency (Hz)  
1 M  
1.5 M  
Frequency (kHz)  
Figure 32.  
Figure 33.  
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GENERAL DESCRIPTION  
SYSTEM CLOCK AND RESET FUNCTIONS  
System Clock Input  
The PCM1795 requires a system clock to operate the digital interpolation filters and advanced segment DAC  
modulators. The system clock is applied at the SCK input (pin 7). The PCM1795 has a system clock detection  
circuit that automatically senses the frequency at which the system clock is operating. Table 2 shows examples  
of system clock frequencies for common audio sampling rates. If the oversampling rate of the delta-sigma (ΔΣ)  
modulator is selected as 128 fS, the system clock frequency is required to be greater than 256 fS.  
Figure 34 and Table 3 show the timing requirements for the system clock input. For optimal performance, it is  
important to use a clock source with low phase jitter and noise. The Texas Instruments PLL1700 family of  
multiclock generators is an excellent choice to provide the PCM1795 system clock.  
Table 2. System Clock Rates for Common Audio Sampling Frequencies  
SYSTEM CLOCK FREQUENCY (fSCK) (MHz)  
SAMPLING FREQUENCY  
(kHz)  
32  
128 fS  
4.096(1)  
5.6488(1)  
6.144(1)  
12.288  
192 fS  
6.144(1)  
8.4672  
9.216  
256 fS  
8.192  
384 fS  
12.288  
512 fS  
16.384  
22.5792  
24.576  
49.152(1)  
X(2)  
768 fS  
24.576  
33.8688  
36.864  
73.728(1)  
X(2)  
44.1  
48  
11.2896  
12.288  
24.576  
49.152(1)  
16.9344  
18.432  
96  
18.432  
36.864  
36.864  
73.728(1)  
192  
24.576  
(1) This system clock rate is not supported in I2C fast mode.  
(2) This system clock rate is not supported for the given sampling frequency.  
t(SCKH)  
High  
2 V  
System Clock  
(SCK)  
0.8 V  
Low  
t(SCKL)  
t(SCY)  
Figure 34. System Clock Input Timing  
Table 3. Timing Characteristics for Figure 34  
PARAMETER  
MIN  
13  
MAX  
UNIT  
ns  
t(SCY)  
System clock pulse cycle time  
System clock pulse duration, high  
System clock pulse duration, low  
t(SCKH)  
t(SCKL)  
0.4t(SCY)  
0.4t(SCY)  
ns  
ns  
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Power-On and External Reset Functions  
The PCM1795 includes a power-on reset function, as shown in Figure 35. With VDD > 2 V, the power-on reset  
function is enabled. The initialization sequence requires 1024 system clocks from the time VDD > 2 V. After the  
initialization period, the PCM1795 is set to its default reset state, as described in the Mode Control Registers  
section.  
The PCM1795 also includes an external reset capability using the RST input (pin 14). This feature allows an  
external controller or master reset circuit to force the PCM1795 to initialize to the default reset state.  
Figure 36 and Table 4 show the external reset operation and timing. The RST pin is set to logic 0 for a minimum  
of 20 ns. The RST pin is then set to a logic 1 state, thus starting the initialization sequence that requires 1024  
system clock periods. The external reset is especially useful in applications where there is a delay between the  
PCM1795 power-up and system clock activation.  
VDD  
2.4 V (Max)  
2 V (Typ)  
1.6 V (Min)  
Reset  
Reset Removal  
Internal Reset  
System Clock  
1024 System Clocks  
Figure 35. Power-On Reset Timing  
RST (Pin 14)  
1.4 V  
t(RST)  
Reset  
Reset Removal  
Internal Reset  
System Clock  
1024 System Clocks  
Figure 36. External Reset Timing  
Table 4. Timing Characteristics for Figure 36  
PARAMETER  
MIN  
20  
MAX  
UNIT  
t(RST)  
Reset pulse duration, low  
ns  
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AUDIO DATA INTERFACE  
Audio Serial Interface  
The audio interface port is a three-wire serial port. It includes LRCK (pin 4), BCK (pin 6), and DATA (pin 5). BCK  
is the serial audio bit clock, and it is used to clock the serial data present on DATA into the serial shift register of  
the audio interface. Serial data are clocked into the PCM1795 on the rising edge of BCK. LRCK is the serial  
audio left/right word clock.  
The PCM1795 requires the synchronization of LRCK and the system clock, but does not need a specific phase  
relation between LRCK and the system clock.  
If the relationship between LRCK and the system clock changes more than ±6 BCK, internal operation is  
initialized within 1/fS and analog outputs are forced to the bipolar zero level until resynchronization between  
LRCK and the system clock is completed.  
PCM Audio Data Formats and Timing  
The PCM1795 supports industry-standard audio data formats, including standard right-justified, I2S, and  
left-justified. The data formats are illustrated in Figure 38 to Figure 40. Data formats are selected using the  
format bits, FMT[2:0], in control register 18. The default data format is 32-bit I2S. All formats require binary twos  
complement, MSB-first audio data. Figure 37 and Table 5 show a detailed timing diagram for the serial audio  
interface.  
1.4 V  
1.4 V  
1.4 V  
LRCK  
t(BCH)  
t(BCL)  
t(LB)  
BCK  
t(BCY)  
t(BL)  
DATA  
t(DS)  
t(DH)  
Figure 37. Audio Interface Timing  
Table 5. Timing Characteristics for Figure 37  
PARAMETER  
MIN  
70  
30  
30  
10  
10  
10  
10  
MAX  
UNIT  
t(BCY)  
t(BCL)  
t(BCH)  
t(BL)  
BCK pulse cycle time  
BCK pulse duration, low  
BCK pulse duration, high  
BCK rising edge to LRCK edge  
LRCK edge to BCK rising edge  
DATA setup time  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
t(LB)  
t(DS)  
t(DH)  
DATA hold time  
LRCK clock data  
50% ± 2 bit clocks  
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1/fS  
Right Channel  
LRCK  
Left Channel  
BCK  
Audio Data Word = 16-Bit, BCK ³ 32 fS  
14 15 16  
1
2
15 16  
LSB  
1
2
15 16  
DATA  
MSB  
Audio Data Word = 24-Bit, BCK ³ 48 fS  
23 24  
1
2
23 24  
LSB  
1
2
23 24  
31 32  
22  
DATA  
MSB  
Audio Data Word = 32-Bit, BCK ³ 64 fS  
30 31 32  
31  
1
2
32  
1
2
DATA  
MSB  
LSB  
Figure 38. Audio Data Input Format: Standard Data Format (Right-Justified), Left Channel = High, Right  
Channel = Low  
1/fS  
Right Channel  
LRCK  
Left Channel  
BCK  
Audio Data Word = 24-Bit, BCK ³ 48 fS  
DATA  
1
2
23 24  
LSB  
1
2
23 24  
1
2
MSB  
Figure 39. Audio Data Input Format: Left-Justified Data Format, Left Channel = High, Right Channel =  
Low  
1/fS  
LRCK  
Left Channel  
Right Channel  
BCK  
Audio Data Word = 24-Bit, BCK ³ 48 fS  
23 24  
LSB  
1
1
2
2
23 24  
1
1
2
2
1
1
2
DATA  
MSB  
Audio Data Word = 32-Bit, BCK ³ 64 fS  
DATA  
2
31 32  
LSB  
31 32  
MSB  
Figure 40. Audio Data Input Format: I2S Data Format, Left Channel = Low, Right Channel = High  
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External Digital Filter Interface and Timing  
The PCM1795 supports an external digital filter interface that consists of a three- or four-wire synchronous serial  
port that allows the use of an external digital filter. External filters include the Texas Instruments’ DF1704 and  
DF1706, the Pacific Microsonics PMD200, or a programmable digital signal processor.  
In the external DF mode, LRCK (pin 4), BCK (pin 6) and DATA (pin 5) are defined as: WDCK, the word clock;  
BCK, the bit clock; and DATA, the monaural data. The external digital filter interface is selected by using the  
DFTH bit of control register 20, which functions to bypass the internal digital filter of the PCM1795.  
When the DFMS bit of control register 19 is set, the PCM1795 can process stereo data. In this case, ZEROL (pin  
1) and ZEROR (pin 2) are defined as left-channel data and right-channel data input, respectively.  
Detailed information for the external digital filter interface mode is provided in the Application For External Digital  
Filter Interface section.  
Direct Stream Digital (DSD) Format Interface and Timing  
The PCM1795 supports the DSD format interface operation, which includes out-of-band noise filtering using an  
internal analog FIR filter. For DSD operation, SCK (pin 7) is redefined as BCK, DATA (pin 5) as DATAL (left  
channel audio data), and LRCK (pin 4) as DATAR (right channel audio data). BCK (pin 6) must be forced low in  
the DSD mode. The DSD format interface is activated by setting the DSD bit of control register 20.  
Detailed information for the DSD mode is provided in the Application For DSD Format (DSD Mode) Interface  
section.  
TDMCA Interface  
The PCM1795 supports the time-division-multiplexed command and audio (TDMCA) data format to enable  
control of and communication with a number of external devices over a single serial interface.  
Detailed information for the TDMCA format is provided in the TDMCA Interface Format section.  
FUNCTION DESCRIPTIONS  
Zero Detect  
The PCM1795 has a zero-detect function. When the PCM1795 detects the zero conditions as shown in Table 6,  
the PCM1795 sets ZEROL (pin 1) and ZEROR (pin 2) high.  
Table 6. Zero Conditions  
MODE  
PCM  
DETECTING CONDITION AND TIME  
DATA is continuously low for 1024 LRCKs.  
External DF mode  
DATA is continuously low for 1024 WDCKs.  
There are an equal number of 1s and 0s in every 8 bits of DSD input data for 23  
ms.  
DZ0  
DZ1  
DSD  
The input data are continuously 1001 0110 for 23 ms.  
SERIAL CONTROL INTERFACE  
The PCM1795 supports both SPI and I2C interfaces that set the mode control registers; see Table 9. The serial  
control interface is selected by MSEL (pin 3); SPI is activated when MSEL is set low, and I2C is activated when  
MSEL is set high.  
SPI Interface  
The SPI interface is a four-wire synchronous serial port that operates asynchronously to the serial audio interface  
and the system clock (SCK). The serial control interface is used to program and read the on-chip mode registers.  
The control interface includes MDO (pin 13), MDI (pin 11), MC (pin 12), and MS (pin 10). MDO is the serial data  
output, used to read back the values of the mode registers; MDI is the serial data input, used to program the  
mode registers; MC is the serial bit clock, used to shift data in and out of the control port; and MS is the mode  
control enable, used to enable the internal mode register access.  
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Register Read/Write Operation  
All read/write operations for the serial control port use 16-bit data words. Figure 41 shows the control data word  
format. The most significant bit (MSB) is the read/write (R/W) bit. For write operations, the R/W bit must be set to  
'0'. For read operations, the R/W bit must be set to '1'. There are seven bits, labeled IDX[6:0], that hold the  
register index (or address) for the read and write operations. The least significant eight bits, D[7:0], contain the  
data to be written to, or the data that was read from, and the register specified by IDX[6:0].  
Figure 42 shows the functional timing diagram for writing or reading the serial control port. MS is held at a logic 1  
state until a register must be written to or read from. To start the register write or read cycle, MS is set to logic 0.  
Sixteen clocks are then provided on MC, corresponding to the 16 bits of the control data word on MDI and  
readback data on MDO. After the eighth clock cycle has completed, the data from the indexed-mode control  
register appears on MDO during the read operation. After the 16th clock cycle has completed, the data are  
latched into the indexed-mode control register during the write operation. To write or read subsequent data, MS  
must be set to '1' once.  
LSB  
D0  
MSB  
R/W  
IDX6  
IDX5  
IDX4  
IDX3  
IDX2  
IDX1  
IDX0  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
Register Index (or Address)  
Register Data  
Figure 41. Control Data Word Format for MDI  
MS  
MC  
MDI  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
D7  
D7  
D6  
D6  
D5  
D5  
D4  
D4  
D3  
D3  
D2  
D2  
D1  
D0  
D0  
R/W  
High Impedance  
MDO  
D1  
When Read Mode is Instructed  
NOTE: Bit 15 is used for selection of write or read. Setting R/W = 0 indicates a write, while R/W = 1 indicates a read. Bits 14–8 are used for  
the register address. Bits 7–0 are used for register data.  
Figure 42. Serial Control Format  
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t(MHH)  
1.4 V  
MS  
t(MSS)  
t(MCH)  
t(MCL)  
t(MSH)  
MC  
1.4 V  
1.4 V  
t(MCY)  
LSB  
MDI  
t(MDS)  
t(MOS)  
t(MDH)  
50% of VDD  
MDO  
Figure 43. Control Interface Timing  
Timing Characteristics for Figure 43  
PARAMETER  
MIN  
100  
40  
MAX  
UNIT  
ns  
t(MCY)  
t(MCL)  
t(MCH)  
t(MHH)  
t(MSS)  
t(MSH)  
t(MDH)  
t(MDS)  
t(MOS)  
MC pulse cycle time  
MC low-level time  
ns  
MC high-level time  
MS high-level time  
40  
ns  
80  
ns  
MS falling edge to MC rising edge  
MS hold time(1)  
15  
ns  
15  
ns  
MDI hold time  
15  
ns  
MDI setup time  
15  
ns  
MC falling edge to MDO stable  
30  
ns  
(1) MC rising edge for LSB to MS rising edge.  
I2C INTERFACE  
The PCM1795 supports the I2C serial bus and the data transmission protocol for standard and fast mode as a  
slave device. This protocol is explained in the I2C specification 2.0.  
In I2C mode, the control terminals are changed as described in Table 7.  
Table 7. Control Terminals  
TERMINAL NAME  
TDMCA NAME  
ADR0  
PROPERTY  
Input  
DESCRIPTION  
I2C address 0  
I2C address 1  
I2C clock  
MS  
MDI  
MC  
ADR1  
Input  
SCL  
Input  
MDO  
SDA  
Input/output  
I2C data  
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Slave Address  
The PCM1795 has seven bits for its own slave address, as shown in Figure 44. The first five bits (MSBs) of the  
slave address are factory preset to 10011. The next two bits of the address byte are the device select bits that  
can be user-defined by the ADR1 and ADR0 terminals. A maximum of four PCM1795s can be connected on the  
same bus at one time. Each PCM1795 responds when it receives its own slave address.  
MSB  
1
LSB  
R/W  
0
0
1
1
ADR1  
ADR0  
Figure 44. Slave Address  
Packet Protocol  
A master device must control packet protocol that consists of a start condition, slave address, read/write bit, data  
if write or acknowledge if read, and stop condition. The PCM1795 supports only slave receivers and slave  
transmitters.  
SDA  
SCL  
St  
17  
8
9
18  
9
18  
9
9
Sp  
Slave Address  
R/W  
ACK  
DATA  
ACK  
DATA  
ACK  
ACK  
R/W: Read Operation if 1; Otherwise, Write Operation  
ACK: Acknowledgment of a Byte if 0  
NACK: Not Acknowledged if 1  
Start  
Condition  
Stop  
Condition  
DATA: 8 Bits (Byte)  
Write Operation  
Transmitter  
Data Type  
M
M
M
S
M
S
M
S
S
M
Sp  
St  
Slave Address  
ACK  
DATA  
ACK  
DATA  
ACK  
ACK  
W
Read Operation  
Transmitter  
Data Type  
M
M
M
S
S
M
S
M
M
M
Sp  
St  
Slave Address  
R
ACK  
DATA  
ACK  
DATA  
ACK  
NACK  
M: Master Device  
S: Slave Device  
St: Start Condition  
Sp: Stop Condition  
R: Read  
W: Write  
ACK: Acknowledge  
NACK: Not Acknowledged  
Figure 45. Basic I2C Framework  
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Write Register  
A master can write to any PCM1795 registers using single or multiple accesses. The master sends a PCM1795  
slave address with a write bit, a register address, and the data. If multiple access is required, the address is that  
of the starting register, followed by the data to be transferred. When the data are received properly, the index  
register is incremented by '1' automatically. When the index register reaches 0x7F, the next value is 0x00. When  
undefined registers are accessed, the PCM1795 does not send an acknowledgment. Figure 46 shows a diagram  
of the write operation.  
S
Transmitter  
Data Type  
M
M
M
S
M
M
S
M
S
S
M
Register Address  
Sp  
St  
Slave Address  
ACK  
ACK  
Write Data 1  
ACK Write Data 2 ACK  
NACK  
W
M: Master Device  
S: Slave Device  
St: Start Condition  
Sp: Stop Condition  
ACK: Acknowledge  
NACK: Not Acknowledged  
W: Write  
Figure 46. Write Operation  
Read Register  
A master can read the PCM1795 register. The value of the register address is stored in an indirect index register  
in advance. The master sends a PCM1795 slave address with a read bit after storing the register address. Then  
the PCM1795 transfers the data that the index register points to. When the data are transferred during a multiple  
access, the index register is incremented by '1' automatically. (When first going into read mode immediately  
following a write, the index register is not incremented. The master can read the register that was previously  
written.) When the index register reaches 0x7F, the next value is 0x00. The PCM1795 outputs some data when  
the index register is 0x10 to 0x1F, even if it is not defined in Table 9. Figure 47 shows a diagram of the read  
operation.  
S
Transmitter  
Data Type  
M
M
M
S
M
M
M
M
S
S
M
M
M
Register Address  
Sp  
St  
Slave Address  
ACK  
ACK Sr  
Slave Address  
R
ACK  
Data  
ACK  
NACK  
W
M: Master Device  
S: Slave Device  
St: Start Condition  
Sr: Repeated Start Condition  
Sp: Stop Condition  
R: Read  
W: Write  
ACK: Acknowledge  
NACK: Not Acknowledged  
Figure 47. Read Operation  
Noise Suppression  
The PCM1795 incorporates noise suppression using the system clock (SCK). However, there must be no more  
than two noise spikes in 600 ns. The noise suppression works for SCK frequencies between 8 MHz and 40 MHz  
in fast mode. However, it works incorrectly under the following conditions:  
Case 1:  
1. t(SCK) > 120 ns (t(SCK): period of SCK)  
2. t(HI) + t(D–HD) < t(SCK) × 5  
3. Spike noise exists on the first half of the SCL high pulse.  
4. Spike noise exists on the SDA high pulse just before SDA goes low.  
SCL  
Noise  
SDA  
Figure 48. Case 1  
When these conditions occur at the same time, the data are recognized as low.  
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Case 2:  
1. t(SCK) > 120 ns  
2. t(S–HD) or t(RS–HD) < t(SCK) × 5  
3. Spike noise exists on both SCL and SDA during the hold time.  
SCL  
Noise  
SDA  
Figure 49. Case 2  
When these conditions occur at the same time, the PCM1795 fails to detect a start condition.  
Case 3:  
1. t(SCK) < 50 ns  
2. t(SP) > t(SCK)  
3. Spike noise exists on SCL just after SCL goes low.  
4. Spike noise exists on SDA just before SCL goes low.  
SCL  
SDA  
Noise  
Figure 50. Case 3  
When these conditions occur at the same time, the PCM1795 erroneously detects a start or stop condition.  
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MODE CONTROL REGISTERS  
User-Programmable Mode Controls  
The PCM1795 includes a number of user-programmable functions that are accessed via mode control registers.  
The registers are programmed using the serial control interface, as previously discussed in the SPI Interface and  
I2C Interface sections. Table 8 lists the available mode-control functions, along with the default reset conditions  
and associated register index.  
Table 8. User-Programmable Function Controls  
DF  
FUNCTION  
Digital attenuation control  
DEFAULT  
REGISTER  
Register 16  
Register 17  
BIT  
PCM  
DSD  
BYPASS  
ATL[7:0] (for left channel)  
ATR[7:0] (for right channel)  
0 dB  
Yes  
No  
No  
0 dB to –120 dB and mute, 0.5-dB step  
Attenuation load control  
Attenuation disabled  
24-bit I2S format  
Register 18  
ATLD  
Yes  
Yes  
No  
No  
No  
Disabled, enabled  
Input audio data format selection  
16-, 20-, 32-bit standard (right-justified)  
format  
Register 18  
FMT[2:0]  
Yes  
24-bit MSB-first left-justified format  
16-/32-bit I2S format  
Sampling rate selection for de-emphasis  
Disabled, 44.1 kHz, 48 kHz, 32 kHz  
De-emphasis control  
De-emphasis disabled  
De-emphasis disabled  
Mute disabled  
Normal  
Register 18  
Register 18  
Register 18  
Register 19  
Register 19  
Register 19  
Register 19  
Register 19  
Register 19  
Register 20  
Register 20  
Register 20  
Register 20  
Register 20  
Register 20  
DMF[1:0]  
DME  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes(1)  
No  
No  
No  
Disabled, enabled  
Soft mute control  
MUTE  
REV  
No  
No  
Soft mute disabled, enabled  
Output phase reversal  
Yes  
No  
Yes  
No  
Normal, reverse  
Attenuation speed selection  
×1fS, ×(1/2)fS, ×(1/4)fS, ×(1/8)fS  
DAC operation control  
×1 fS  
ATS[1:0]  
OPE  
DAC operation enabled  
Monaural  
Yes  
No  
Yes  
Yes  
No  
Enabled, disabled  
Stereo DF bypass mode select  
Monaural, stereo  
DFMS  
FLT  
Digital filter roll-off selection  
Sharp roll-off, slow roll-off  
Infinite zero mute control  
Disabled, enabled  
Sharp roll-off  
Disabled  
No  
INZD  
No  
Yes  
Yes  
No  
System reset control  
Normal operation  
Disabled  
SRST  
DSD  
Yes  
Yes  
No  
Reset operation, normal operation  
DSD interface mode control  
DSD enabled, disabled  
Digital-filter bypass control  
DF enabled, DF bypass  
Monaural mode selection  
Stereo, monaural  
DF enabled  
Stereo  
DFTH  
MONO  
CHSL  
OS[1:0]  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes(2)  
Channel selection for monaural mode data  
Left channel, Right channel  
ΔΣ oversampling rate selection  
×64 fS, ×128 fS, ×32 fS  
Left channel  
×64 fS  
PCM zero output enable  
DSD zero output enable  
Enabled  
Disabled  
Register 21  
Register 21  
PCMZ  
Yes  
Yes  
No  
Yes  
No  
DZ[1:0]  
Yes  
(1) When in DSD mode, DMF[1:0] is defined as DSD filter (analog FIR) performance selection.  
(2) When in DSD mode, OS[1:0] is defined as DSD filter (analog FIR) operating rate selection.  
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Table 8. User-Programmable Function Controls (continued)  
DF  
FUNCTION  
FUNCTION AVAILABLE ONLY FOR READ  
Zero detection flag  
DEFAULT  
REGISTER  
BIT  
PCM  
DSD  
BYPASS  
Not zero = 0  
ZFGL (for left channel)  
ZFGR (for right channel)  
ID[4:0]  
Register 22  
Register 23  
Yes  
Yes  
Yes  
No  
Yes  
No  
Not zero, zero detected  
Zero detected = 1  
Device ID (at TDMCA)  
Register Map  
The mode control register map is shown in Table 9. Registers 16 to 21 include an R/W bit that determines  
whether a register read (R/W = 1) or write (R/W = 0) operation is performed. Registers 22 and 23 are read-only.  
Table 9. Mode Control Register Map  
REGISTER  
Register 16  
Register 17  
Register 18  
Register 19  
Register 20  
Register 21  
Register 22  
Register 23  
B15  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R
B14  
0
B13  
0
B12  
1
B11  
0
B10  
0
B9  
0
B8  
0
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
ATL7  
ATL6  
ATL5  
ATL4  
ATL3  
ATL2  
ATL1  
ATL0  
0
0
1
0
0
0
1
ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0  
0
0
1
0
0
1
0
ATLD FMT2 FMT1 FMT0 DMF1 DMF0  
DME  
FLT  
MUTE  
INZD  
OS0  
0
0
1
0
0
1
1
REV  
RSV  
RSV  
RSV  
RSV  
ATS1  
SRST  
RSV  
ATS0  
DSD  
RSV  
RSV  
RSV  
OPE  
RSV  
DFMS  
0
0
1
0
1
0
0
DFTH MONO CHSL  
OS1  
DZ0  
0
0
1
0
1
0
1
RSV  
RSV  
ID4  
RSV  
RSV  
ID3  
DZ1  
RSV  
ID2  
PCMZ  
0
0
1
0
1
1
0
RSV  
ZFGR ZFGL  
ID1 ID0  
R
0
0
1
0
1
1
1
RSV  
Register Definitions  
B14  
B13  
B12  
B11  
B10  
B9  
B8  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
B15  
Register 16  
Register 17  
0
0
0
1
0
0
0
0
0
1
ATL7  
ATL6  
ATL5  
ATL4  
ATR4  
ATL3  
ATR3  
ATL2  
ATR2  
ATL1  
ATR1  
ATL0  
ATR0  
R/W  
0
1
0
0
ATR7  
ATR6  
ATR5  
R/W  
R/W: Read/Write Mode Select  
When R/W = 0, a write operation is performed.  
When R/W = 1, a read operation is performed.  
Default value: 0  
ATx[7:0]: Digital Attenuation Level Setting  
These bits are available for read and write.  
Default value: 1111 1111b  
Each DAC output has a digital attenuator associated with it. The attenuator can be set from 0 dB to –120 dB, in  
0.5-dB steps. Alternatively, the attenuator can be set to infinite attenuation (or mute). The attenuation data for  
each channel can be set individually. However, the data load control (the ATLD bit of control register 18) is  
common to both attenuators. ATLD must be set to '1' in order to change an attenuator setting. The attenuation  
level can be set using Equation 1:  
Attenuation level (dB) = 0.5 dB × (ATx[7:0]DEC – 255)  
Where,  
ATx[7:0]DEC = 0 through 255  
For ATx[7:0]DEC = 0 through 14, the attenuator is set to infinite attenuation. Table 10 lists the attenuation levels  
for various settings.  
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Table 10. Attenuation Levels  
ATx[7:0]  
1111 1111b  
1111 1110b  
1111 1101b  
DECIMAL VALUE  
ATTENUATION LEVEL SETTING  
0 dB, no attenuation (default)  
255  
254  
253  
–0.5 dB  
–1.0 dB  
0001 0000b  
0000 1111b  
0000 1110b  
16  
15  
14  
–119.5 dB  
–120.0 dB  
Mute  
0000 0000b  
0
Mute  
B14  
B13  
B12  
B11  
B10  
B9  
B8  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
B15  
Register 18  
0
0
1
0
0
1
0
ATLD  
FMT2 FMT1 FMT0 DMF1 DMF0  
DME MUTE  
R/W  
R/W: Read/Write Mode Select  
When R/W = 0, a write operation is performed.  
When R/W = 1, a read operation is performed.  
Default value: 0  
ATLD: Attenuation Load Control  
This bit is available for read and write.  
Default value: 0  
ATLD  
Attenuation Control Setting  
ATLD = 0  
ATLD = 1  
Attenuation control disabled (default)  
Attenuation control enabled  
The ATLD bit is used to enable loading of the attenuation data contained in registers 16 and 17. When ATLD =  
0, the attenuation settings remain at the previously programmed levels, ignoring new data loaded from registers  
16 and 17. When ATLD = 1, attenuation data written to registers 16 and 17 is loaded normally.  
FMT[2:0]: Audio Interface Data Format  
These bits are available for read and write.  
Default value: 101  
FMT[2:0]  
000  
Audio Data Format Selection  
16-bit standard format, right-justified data, BCK x32 fS  
32-bit standard format, right-justified data, BCK x64 fS  
24-bit standard format, right-justified data, BCK x48 fS  
24-bit MSB-first, left-justified format data, BCK x48 fS  
32-bit I2S format data, BCK x64 fS  
001  
010  
011  
100  
101  
24-bit I2S format data (default), BCK x48 fS  
110  
Reserved  
111  
Reserved  
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The FMT[2:0] bits are used to select the data format for the serial audio interface.  
For the external digital filter interface mode (DFTH mode), this register is operated as shown in the Application  
for External Digital Filter Interface section.  
DMF[1:0]: Sampling Frequency Selection for the De-Emphasis Function  
These bits are available for read and write.  
Default value: 00  
DMF[1:0]  
De-Emphasis Sampling Frequency Selection  
00  
01  
10  
11  
Disabled (default)  
48 kHz  
44.1 kHz  
32 kHz  
The DMF[1:0] bits are used to select the sampling frequency used by the digital de-emphasis function when it is  
enabled by setting the DME bit. The de-emphasis curves are shown in the Typical Characteristics section.  
For the DSD mode, analog FIR filter performance can be selected using this register. A register map and filter  
response plots are shown in the Application For DSD Format (DSD Mode) Interface section.  
DME: Digital De-Emphasis Control  
This bit is available for read and write.  
Default value: 0  
DME  
De-Emphasis Setting  
DME = 0  
DME = 1  
De-emphasis disabled (default)  
De-emphasis enabled  
The DME bit is used to enable or disable the de-emphasis function for both channels.  
MUTE: Soft Mute Control  
This bit is available for read and write.  
Default value: 0  
MUTE  
Soft Mute Setting  
MUTE = 0  
MUTE = 1  
Soft mute disabled (default)  
Soft mute enabled  
The MUTE bit is used to enable or disable the soft mute function for both channels.  
Soft mute is operated as a 256-step attenuator. The speed for each step to –dB (mute) is determined by the  
attenuation rate selected in the ATS register.  
B14  
B13  
B12  
B11  
B10  
B9  
B8  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
B15  
Register 19  
0
0
1
0
0
1
1
REV  
ATS1  
ATS0  
OPE  
RSV  
DMFS  
FLT  
INZD  
R/W  
R/W: Read/Write Mode Select  
When R/W = 0, a write operation is performed.  
When R/W = 1, a read operation is performed.  
Default value: 0  
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REV: Output Phase Reversal  
This bit is available for read and write.  
Default value: 0  
REV  
Output Setting  
REV = 0  
REV = 1  
Normal output (default)  
Inverted output  
The REV bit is used to invert the output phase for both channels.  
ATS[1:0]: Attenuation Rate Select  
These bits are available for read and write.  
Default value: 00  
ATS[1:0]  
Attenuation Rate Selection  
00  
01  
10  
11  
Every LRCK (default)  
LRCK/2  
LRCK/4  
LRCK/8  
The ATS[1:0] bits are used to select the rate at which the attenuator is decremented/incremented during level  
transitions.  
OPE: DAC Operation Control  
This bit is available for read and write.  
Default value: 0  
OPE  
DAC Operation Control  
OPE = 0  
OPE = 1  
DAC operation enabled (default)  
DAC operation disabled  
The OPE bit is used to enable or disable the analog output for both channels. Disabling the analog outputs  
forces them to the bipolar zero level (BPZ) even if audio data are present on the input.  
DFMS: Stereo DF Bypass Mode Select  
This bit is available for read and write.  
Default value: 0  
DFMS  
Mode Selection  
DFMS = 0  
DFMS = 1  
Monaural (default)  
Stereo input enabled  
The DFMS bit is used to enable stereo operation in DF bypass mode. In the DF bypass mode, when DFMS is  
set to '0', the pin for the input data are DATA (pin 5) only; therefore, the PCM1795 operates as a monaural DAC.  
When DFMS is set to '1', the PCM1795 can operate as a stereo DAC with inputs of the left channel and right  
channel data on ZEROL (pin 1) and ZEROR (pin 2), respectively.  
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FLT: Digital Filter Roll-Off Control  
This bit is available for read and write.  
Default value: 0  
FLT  
Roll-Off Control  
FLT = 0  
FLT = 1  
Sharp roll-off (default)  
Slow roll-off  
The FLT bit is used to select the digital filter roll-off characteristic. The filter responses for these selections are  
shown in the Typical Characteristics section.  
INZD: Infinite Zero Detect Mute Control  
This bit is available for read and write.  
Default value: 0  
INZD  
Infinite Zero Detect Mute Setting  
Infinite zero detect mute disabled (default)  
Infinite zero detect mute enabled  
INZD = 0  
INZD = 1  
The INZD bit is used to enable or disable the zero detect mute function. Setting INZD to '1' forces muted analog  
outputs to hold a bipolar zero level when the PCM1795 detects a zero condition in both channels. The infinite  
zero detect mute function is not available in the DSD mode.  
B14  
B13  
B12  
B11  
B10  
B9  
B8  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
B15  
Register 20  
0
0
1
0
1
0
0
RSV  
SRST  
DSD  
DFTH MONO CHSL  
OS1  
OS0  
R/W  
R/W: Read/Write Mode Select  
When R/W = 0, a write operation is performed.  
When R/W = 1, a read operation is performed.  
Default value: 0  
SRST: System Reset Control  
This bit is available for write only.  
Default value: 0  
SRST  
System Reset Control  
SRST = 0  
SRST = 1  
Normal operation (default)  
System reset operation (generate one reset pulse)  
The SRST bit is used to reset the PCM1795 to the initial system condition.  
DSD: DSD Interface Mode Control  
This bit is available for read and write.  
Default value: 0  
DSD  
DSD Interface Mode Control  
DSD = 0  
DSD = 1  
DSD interface mode disabled (default)  
DSD interface mode enabled  
The DSD bit is used to enable or disable the DSD interface mode.  
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DFTH: Digital Filter Bypass (or Through Mode) Control  
This bit is available for read and write.  
Default value: 0  
DFTH  
Digital Filter Control  
DFTH = 0  
DFTH = 1  
Digital filter enabled (default)  
Digital filter bypassed for external digital filter  
The DFTH bit is used to enable or disable the external digital filter interface mode.  
MONO: Monaural Mode Selection  
This bit is available for read and write.  
Default value: 0  
MONO  
Mode Selection  
MONO = 0  
MONO = 1  
Stereo mode (default)  
Monaural mode  
The MONO function is used to change operation mode from the normal stereo mode to the monaural mode.  
When the monaural mode is selected, both DACs operate in a balanced mode for one channel of audio input  
data. Channel selection is available for left-channel or right-channel data, determined by the CHSL bit.  
CHSL: Channel Selection for Monaural Mode  
This bit is available for read and write.  
Default value: 0  
CHSL  
Channel Selection  
CHSL = 0  
CHSL = 1  
Left channel selected (default)  
Right channel selected  
This bit is available when MONO = 1.  
The CHSL bit selects left-channel or right-channel data to be used in monaural mode.  
OS[1:0]: ΔΣ Oversampling Rate Selection  
These bits are available for read and write.  
Default value: 00  
OS[1:0]  
00  
Operating Speed Selection  
64 times fS (default)  
32 times fS  
01  
10  
128 times fS  
Reserved  
11  
The OS bits are used to change the oversampling rate of ΔΣ modulation. Use of this function enables the  
designer to stabilize the conditions at the post low-pass filter for different sampling rates. As an application  
example, programming to set 128 times in 44.1-kHz operation, 64 times in 96-kHz operation, or 32 times in  
192-kHz operation allows the use of only a single type (cut-off frequency) of post low-pass filter. The 128-fS  
oversampling rate is not available at sampling rates above 100 kHz. If the 128-fS oversampling rate is selected, a  
system clock of more than 256 fS is required.  
In DSD mode, these bits are used to select the speed of the bit clock for DSD data coming into the analog FIR  
filter.  
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B14  
B13  
B12  
B11  
B10  
B9  
B8  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
B15  
Register 21  
0
0
1
0
1
0
1
RSV  
RSV  
RSV  
RSV  
RSV  
DZ1  
DZ0  
PCMZ  
R/W  
R/W: Read/Write Mode Select  
When R/W = 0, a write operation is performed.  
When R/W = 1, a read operation is performed.  
Default value: 0  
DZ[1:0]: DSD Zero Output Enable  
These bits are available for read and write.  
Default value: 00  
DZ[1:0]  
Zero Output Enable  
00  
01  
Disabled (default)  
Even pattern detect 1 × 96h pattern detect  
The DZ bits are used to enable or disable the output zero flags and to select the zero pattern in DSD mode.  
PCMZ: PCM Zero Output Enable  
These bits are available for read and write.  
Default value: 1  
PCMZ  
PCM Zero Output Setting  
PCMZ = 0  
PCMZ = 1  
PCM zero output disabled  
PCM zero output enabled (default)  
The PCMZ bit is used to enable or disable the output zero flags in PCM mode and the external DF mode.  
B14  
B13  
B12  
B11  
B10  
B9  
B8  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
B15  
Register 22  
0
0
1
0
1
1
0
RSV  
RSV  
RSV  
RSV  
RSV  
RSV  
ZFGR ZFGL  
R
R: Read Mode Select  
Value is always '1', specifying the readback mode.  
ZFGx: Zero-Detection Flag  
Where x = L or R, corresponding to the DAC output channel. These bits are available only for readback.  
Default value: 00  
ZFGx  
Zero Detection  
ZFGx = 0  
ZFGx = 1  
Not zero  
Zero detected  
These bits show zero conditions. The status is the same as that of the zero flags at ZEROL (pin 1) and ZEROR  
(pin 2). See Zero Detect in the Function Descriptions section.  
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B14  
B13  
B12  
B11  
B10  
B9  
B8  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
B15  
Register 23  
0
0
1
0
1
1
1
RSV  
RSV  
RSV  
ID4  
ID3  
ID2  
ID1  
ID0  
R
Read Mode Select  
Value is always '1', specifying the readback mode.  
ID[4:0]: Device ID  
The ID[4:0] bits hold a device ID in the TDMCA mode.  
APPLICATION INFORMATION  
TYPICAL CONNECTION DIAGRAM IN PCM MODE  
Figure 51 shows a typical application circuit for PCM mode operation.  
CF  
RF  
5 V  
0.1 mF  
ZEROL  
ZEROR  
MSEL  
LRCK  
DATA  
BCK  
VCC2L  
AGND3L  
IOUTL–  
1
2
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
+
10 mF  
+
Differential-  
to-Single  
Converter  
With  
3
CF  
RF  
VOUT  
IOUTL+  
4
Left Channel  
5 V  
Low-Pass  
Filter  
PCM  
Audio  
Data  
AGND2  
5
VCC  
VCOM  
VCOM  
IREF  
1
6
Source  
+
47 mF  
+
SCK  
L
7
CF  
RF  
10 mF  
PCM1796  
DGND  
VDD  
R
8
0.1 mF  
10 kW  
9
MS  
AGND1  
IOUTR–  
10  
11  
12  
13  
14  
+
Differential-  
to-Single  
Converter  
With  
MDI  
CF  
RF  
VOUT  
Controller  
MC  
IOUTR+  
Right Channel  
0.1 mF  
Low-Pass  
Filter  
AGND3R  
VCC2R  
MDO  
RST  
+
5 V  
10 mF  
+
10 mF  
3.3 V  
Figure 51. Typical Application Circuit for Standard PCM Audio Operation  
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APPLICATION CIRCUIT  
The design of the application circuit is very important in order to actually realize the high S/N ratio of which the  
PCM1795 is capable, because noise and distortion that are generated in an application circuit are not negligible.  
In the third-order, low-pass filter (LPF) circuit of Figure 52, the output level of 2.1 V RMS and 123-dB  
signal-to-noise ratio is achieved.  
Figure 53 shows a circuit for the DSD mode, which is a fourth-order LPF in order to reduce the out-of-band  
noise.  
I/V Section  
The current of the PCM1795 on each of the output pins (IOUTL+, IOUTL–, IOUTR+, IOUTR–) is 4 mAPP at 0 dB  
(full-scale). The voltage output level of the current-to-voltage (I/V) converter, VI, is given by Equation 2:  
VI = 4 mAPP × RF  
Where:  
RF = feedback resistance of the I/V converter  
An NE5534 operational amplifier is recommended for the I/V circuit to obtain the specified performance. Dynamic  
performance such as the gain bandwidth, settling time, and slew rate of the operational amplifier affects the  
audio dynamic performance of the I/V section.  
Differential Section  
The PCM1795 voltage outputs are followed by differential amplifier stages that sum the differential signals for  
each channel, creating a single-ended I/V op-amp output. In addition, the differential amplifiers provide a  
low-pass filter function.  
The operational amplifier recommended for the differential circuit is the low-noise type.  
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C1  
2700 pF  
R1  
820 W  
VCC  
VCC  
C11  
0.1 mF  
R5  
C15  
C3  
200 W  
0.1 mF  
8200 pF  
C17  
22 pF  
7
C19  
5
R3  
R7  
22 pF  
7
2
3
8
6
IOUT-  
220 W  
5
180 W  
R9  
2
3
8
6
100 W  
C5  
27000 pF  
+
U1  
NE5534  
+
U3  
4
NE5534  
C12  
4
R4  
R8  
0.1 mF  
C16  
220 W  
180 W  
R6  
200 W  
0.1 mF  
C4  
VEE  
8200 pF  
VEE  
C2  
2700 pF  
R2  
820 W  
VCC  
C13  
0.1 mF  
C18  
22 pF  
7
5
2
3
8
6
IOUT+  
+
U2  
NE5534  
4
C14  
0.1 mF  
VEE  
Figure 52. Measurement Circuit for PCM  
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C1  
2200 pF  
R1  
820 W  
VCC  
VCC  
C11  
0.1 mF  
R5  
C15  
C5  
150 W  
0.1 mF  
8200 pF  
C17  
22 pF  
7
C19  
5
R3  
R8  
R10  
22 pF  
7
2
3
8
6
IOUT-  
91 W  
75 W  
5
120 W  
R7  
2
3
8
6
100W  
C3  
C4  
27000 pF  
+
U1  
22000 pF  
NE5534  
+
U3  
4
NE5534  
C12  
4
R4  
R9  
R11  
0.1 mF  
C16  
91 W  
75 W  
120 W  
R6  
150 W  
0.1 mF  
C6  
VEE  
8200 pF  
VEE  
C2  
2200 pF  
R2  
820 W  
VCC  
C13  
0.1 mF  
C18  
22 pF  
7
5
2
3
8
6
IOUT+  
+
U2  
NE5534  
4
C14  
0.1 mF  
VEE  
Figure 53. Measurement Circuit for DSD  
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IOUTL- (Pin 26)  
IOUT  
-
OUT+  
Circuit(1)  
IOUTL+ (Pin 25)  
IOUT+  
3
2
1
IOUTR- (Pin 18)  
IOUT  
-
OUT-  
Circuit(1)  
Balanced Out  
IOUTR+ (Pin 17)  
IOUT+  
(1) Circuit corresponds to Figure 52.  
Figure 54. Measurement Circuit for Monaural Mode  
APPLICATION FOR EXTERNAL DIGITAL FILTER INTERFACE  
Figure 55 shows the connection diagram for an external digital filter.  
DFMS = 0  
External Filter Device  
PCM1796  
1
2
3
4
5
6
7
ZEROL  
ZEROR  
MSEL  
LRCK  
DATA  
BCK  
WDCK (Word Clock)  
DATA  
BCK  
SCK  
SCK  
DFMS = 1  
External Filter Device  
DATA_L  
PCM1796  
1
2
3
4
5
6
7
ZEROL  
ZEROR  
MSEL  
LRCK  
DATA  
DATA_R  
WDCK (Word Clock)  
BCK  
SCK  
BCK  
SCK  
Figure 55. Connection Diagram for External Digital Filter (Internal DF Bypass Mode) Application  
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Application for Interfacing With an External Digital Filter  
For some applications, it may be desirable to use an external digital filter to perform the interpolation function, as  
it can provide improved stop-band attenuation when compared to the internal digital filter of the PCM1795.  
The PCM1795 supports several external digital filters, including:  
Texas Instruments DF1704 and DF1706  
Pacific Microsonics PMD200 HDCD filter/decoder IC  
Programmable digital signal processors (DSPs)  
The external digital filter application mode is accessed by programming the following bits in the corresponding  
control register:  
DFTH = 1 (register 20)  
The pins used to provide the serial interface for the external digital filter are illustrated in Figure 55. The word  
clock (WDCK) signal must be operated at 8 times or 4 times the desired sampling frequency, fS.  
Pin Assignment When Using the External Digital Filter Interface  
LRCK (pin 4): WDCK as word clock input  
BCK (pin 6): Bit clock for audio data  
DATA (pin 5): Monaural audio data input when the DFMS bit is not set to '1'  
ZEROL (pin 1): DATAL as left channel audio data input when the DFMS bit is set to '1'  
ZEROR (pin 2): DATAR as right channel audio data input when the DFMS bit is set to '1'  
Audio Format  
The PCM1795 in the external digital filter interface mode supports right-justified audio formats including 16-bit,  
24-bit, and 32-bit audio data, as shown in Figure 56. The audio format is selected by the FMT[2:0] bits of control  
register 18.  
1/4 fS or 1/8 fS  
WDCK  
BCK  
Audio Data Word = 16-Bit  
DATA,DATAL, DATAR  
15 16  
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16  
MSB  
LSB  
Audio Data Word = 32-Bit  
DATA,DATAL, DATAR  
31 32  
1
2
3
4
5
19 20 21 22 23 24 25 26 27 28 29 30 31 32  
MSB  
LSB  
Audio Data Word = 24-Bit  
DATA,DATAL, DATAR  
23 24  
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24  
MSB  
LSB  
Figure 56. Audio Data Input Format for External Digital Filter (Internal DF Bypass Mode) Application  
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System Clock (SCK) and Interface Timing  
The PCM1795 in an application using an external digital filter requires the synchronization of WDCK and the  
system clock. The system clock is phase-free with respect to WDCK. Interface timing among WDCK, BCK,  
DATA, DATAL, and DATAR is shown in Figure 57 and Table 11.  
WDCK  
1.4 V  
1.4 V  
1.4 V  
t(BCH)  
t(BCL)  
t(LB)  
BCK  
t(BCY)  
t(BL)  
DATA  
DATAL  
DATAR  
t(DS)  
t(DH)  
Figure 57. Audio Interface Timing for External Digital Filter (Internal DF Bypass Mode) Application  
Table 11. Timing Characteristics for Figure 57  
PARAMETER  
BCK pulse cycle time  
MIN  
20  
7
MAX  
UNIT  
ns  
t(BCY)  
t(BCL)  
t(BCH)  
t(BL)  
BCK pulse duration, low  
ns  
BCK pulse duration, high  
7
ns  
BCK rising edge to WDCK falling edge  
WDCK falling edge to BCK rising edge  
DATA, DATAL, DATAR setup time  
DATA, DATAL, DATAR hold time  
5
ns  
t(LB)  
5
ns  
t(DS)  
t(DH)  
5
ns  
5
ns  
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FUNCTIONS AVAILABLE IN THE EXTERNAL DIGITAL FILTER MODE  
The external digital filter mode is selected by setting DSD = 0 (register 20, B5) and DFTH = 1 (register 20, B4).  
The external digital filter mode allows access to the majority of the PCM1795 mode control functions.  
Table 12 shows the register mapping available when the external digital filter mode is selected, along with  
descriptions of functions that are modified when using this mode selection.  
Table 12. External Digital Filter Register Map  
REGISTER  
Register 16  
Register 17  
Register 18  
Register 19  
Register 20  
Register 21  
Register 22  
B15  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R
B14  
0
B13  
0
B12  
1
B11  
0
B10  
0
B9  
0
B8  
0
B7  
X(1)  
X
B6  
X
B5  
X
B4  
X
B3  
X
B2  
B1  
X
B0  
X
X
X
0
0
1
0
0
0
1
X
X
X
X
X
X
0
0
1
0
0
1
0
X
FMT2 FMT1 FMT0  
X
X
X
X
0
0
1
0
0
1
1
REV  
X
X
SRST  
X
X
0
OPE  
1
X
DFMS  
X
INZD  
OS0  
PCMZ  
0
0
1
0
1
0
0
MONO CHSL  
OS1  
X
0
0
1
0
1
0
1
X
X
X
X
X
X
X
X
0
0
1
0
1
1
0
X
X
X
ZFGR ZFGL  
(1) Function is disabled. No operation even if data bit is set.  
FMT[2:0]: Audio Data Format Selection  
Default value: 000  
FMT[2:0]  
Audio Data Format Selection  
000  
001  
16-bit right-justified format  
32-bit right-justified format  
010  
24-bit right-justified format (default)  
N/A  
Other  
OS[1:0]: ΔΣ Modulator Oversampling Rate Selection  
Default value: 00  
OS[1:0]  
Operation Speed Selection  
00  
01  
10  
11  
8 times WDCK (default)  
4 times WDCK  
16 times WDCK  
Reserved  
The effective oversampling rate is determined by the oversampling performed by both the external digital filter  
and the ΔΣ modulator. For example, if the external digital filter is 8× oversampling, and OS[1:0] = 00 is selected,  
then the ΔΣ modulator oversamples by 8×, resulting in an effective oversampling rate of 64×. The 16× WDCK  
oversampling rate is not available above a 100-kHz sampling rate. If the oversampling rate selected is 16×  
WDCK, the system clock frequency must be over 256 fS.  
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APPLICATION FOR DSD FORMAT (DSD MODE) INTERFACE  
Figure 58 shows a connection diagram for DSD mode.  
DSD Decoder  
PCM1796  
1
2
3
4
5
6
7
ZEROL  
ZEROR  
MSEL  
LRCK  
DATA  
DATA_R  
DATA_L  
BCK  
Bit Clock  
SCK  
Figure 58. Connection Diagram in DSD Mode  
Feature  
This mode is used for interfacing directly to a DSD decoder, which is found in Super Audio CD™ (SACD)  
applications.  
The DSD mode is accessed by programming the following bit in the corresponding control register.  
DSD = 1 (register 20)  
The DSD mode provides a low-pass filtering function. The filtering is provided using an analog FIR filter structure.  
Four FIR responses are available and are selected by the DMF[1:0] bits of control register 18.  
The DSD bit must be set before inputting DSD data; otherwise, the PCM1795 erroneously detects the TDMCA  
mode and commands are not accepted through the serial control interface.  
Pin Assignment When Using DSD Format Interface  
Several pins are redefined for DSD mode operation. These include:  
DATA (pin 5): DSDL as left-channel DSD data input  
LRCK (pin 4): DSDR as right-channel DSD data input  
SCK (pin 7): DBCK as bit clock for DSD data  
BCK (pin 6): Set low (N/A)  
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Requirements for System Clock  
For operation in DSD mode, the bit clock (DBCK) i