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TDA7529

RF front-end for AM/FM DSP car-radio with IF sampling

Features

■ Fully integrated VCO for world tuning

■ High performance PLL for fast RDS system

■ I/Q mixer for FM IF 10.7MHz with image

rejection and integrated LNA

■ I/Q mixer for AM IF 10.7MHz up conversion

LQFP64

with high dynamic range

■ Integrated balun, Which allows saving of

external mixer tank

■ RF AGC, IF AGC, DAGC

■ Low noise IF amplifier with switched wide

Description

dynamic AGC range

The front-end is a high performance tuner circuit

for AM/FM - DSP car-radios with 10.7MHz IF

sampling. It contains mixer and IF amplifiers for

AM and FM, fully integrated VCO and PLL

synthesizer on a single chip. Use of BiCMOS

technology allows the implementation of several

tuning functions and a minimum of external

components.

■ IF switch for FM / AM / IBOC

■ Electronic alignment for the preselection

stages

2

■ I C/SPI controlled

■ single 5v SUPPLY

■ Alternative frequency control signals to DSP

Table 1.

Device summary

Part number

Package

Packing

TDA7529

LQFP64 exposed pad (10x10x1.4)

Tray

TDA7529TR

Tape and reel

March 2007

Rev 1

1/60

www.st.com

1

Contents

TDA7529

Contents

1

2

3

Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Function description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

IMR Mixer and active balun output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

FM RF-AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

AM RF-AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

IF AGC and IF amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

D/A Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

FREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.10 GPIO - general purpose IO interface pins . . . . . . . . . . . . . . . . . . . . . . . . 16

3.11 AFSAMPLE/AFHOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.12 Serial BUS interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4

Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

General key parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

FM - section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

AM - section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

IF - section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Reference frequency input buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.10 Phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.11 Phase frequency detector and charge pump . . . . . . . . . . . . . . . . . . . . . . 25

4.12 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.13 D/A-Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2/60

TDA7529

Contents

4.14 A/D-Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.15 GPIO – general purpose IO interface pins . . . . . . . . . . . . . . . . . . . . . . . . 27

4.16 AFSAMPLE / AFHOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.17 Serial Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5

Tuning state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.1

Tuning state machine modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.1.1

5.1.2

5.1.3

5.1.4

5.1.5

Mode 000: buffer (nil) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Mode 001: preset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Mode 010: search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Mode 011: AF update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Mode 100: jump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.2

5.3

5.4

5.5

5.6

Mode 100: check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Mode 110: load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Mode 111: end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Register SWAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

State machine start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6

Registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6.1

Data byte specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6.1.1

6.1.2

6.1.3

6.1.4

6.1.5

6.1.6

6.1.7

6.1.8

6.1.9

Short_reg (0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

ADCctrl (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

GPIO mode (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

AGC and mixer control (3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Register (4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Divider R (5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

IF AGC control (6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

FM AGC (7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

AGC voltage threshold (8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

6.1.10 Mixer alignment 1 (9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

6.1.11 Mixer alignment 2 (10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6.1.12 PLL control 1 (11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

6.1.13 PLL control 2 (12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

6.1.14 PLL test (13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

6.1.15 Misc 2 (14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

6.1.16 WAIT LOCK (15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3/60

Contents

TDA7529

6.1.17 AGC time constant settings (16 / 32) . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

6.1.18 AMAGC control (17 / 33) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.1.19 GPIO output level control (18 / 34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

6.1.20 IF control (19 / 35) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

6.1.21 AF state machine wait time 1 (20 / 36) . . . . . . . . . . . . . . . . . . . . . . . . . 50

6.1.22 PLL main divider (N-divider) 1 (21 / 37) . . . . . . . . . . . . . . . . . . . . . . . . . 50

6.1.23 PLL main divider (N-divider) 2 (22 / 38) . . . . . . . . . . . . . . . . . . . . . . . . . 50

6.1.24 PLL main divider (N-divider) 3 (23 / 39) . . . . . . . . . . . . . . . . . . . . . . . . . 51

6.1.25 PLL Divider ratio calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6.1.26 VCO divider (V-divider) (24 / 40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6.1.27 Charge pump current (25 / 41) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

6.1.28 Tuning DAC 1 (26 / 42) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

6.1.29 Tuning DAC 2 (27 / 43) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

6.1.30 DAC output voltage = 600mV + DACval * 9mV . . . . . . . . . . . . . . . . . . . 53

6.1.31 Different controls (28 / 44) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

6.1.32 Misc 3 (29 / 45) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

6.1.33 Analog test select (30 / 46) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

6.1.34 AD converter test (31 / 47) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

6.1.35 Read 1 (48) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

6.1.36 Read 2 (49) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

7

8

9

Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

4/60

TDA7529

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

IF AGC and IF amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Switching frequency as a function of the process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

GPIO - general purpose IO interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2

Supports data communication using the SPI and the I C protocol. . . . . . . . . . . . . . . . . . . 17

2

I C addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 8.

Table 9.

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

General key parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

FM - section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

AM - section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

IF - section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Reference frequency input buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Dividers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Phase frequency detector and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

D/A-Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

A/D-Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

GPIO - general purpose IO interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

AFSAMPLE / AFHOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Serial Data Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Values of the programmable wait times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Short_reg (0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

ADCctrl (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

GPIO mode (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

AGC and mixer control (3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Register (4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Divider R (5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

IF AGC control (6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

FM AGC (7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

AGC voltage threshold (8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Mixer alignment 1 (9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Mixer alignment 2 (10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

PLL control 1 (11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

PLL control 2 (12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

PLL test (13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Misc 2 (14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

WAIT LOCK (15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

AGC time constant settings (16 / 32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

AMAGC control (17 / 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

GPIO output level control (18 / 34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

IF control (19 / 35) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

AF state machine wait time 1 (20 / 36) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

PLL main divider (N-divider) 1 (21 / 37) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

PLL main divider (N-divider) 2 (22 / 38) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Table 24.

Table 25.

Table 26.

Table 27.

Table 28.

Table 29.

Table 30.

Table 31.

Table 32.

Table 33.

Table 34.

Table 35.

Table 36.

Table 37.

Table 38.

Table 39.

Table 40.

Table 41.

Table 42.

Table 43.

Table 44.

Table 45.

Table 46.

Table 47.

Table 48.

5/60

List of tables

TDA7529

Table 49.

Table 50.

Table 51.

Table 52.

Table 53.

Table 54.

Table 55.

Table 56.

Table 57.

Table 58.

Table 59.

Table 60.

Table 61.

PLL main divider (N-divider) 3 (23 / 39) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

PLL Divider ratio calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

VCO divider (V-divider) (24 / 40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Charge pump current (25 / 41) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Tuning DAC 1 (26 / 42). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Tuning DAC 2 (27 / 43). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Different controls (28 / 44) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Misc 3 (29 / 45) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Analog test select (30 / 46). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

AD converter test (31 / 47) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Read 1 (48). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Read 2 (49). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

6/60

TDA7529

List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Positive current diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Positive/negative current diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Voltage and current mode with hand-over . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2

I C (sub address mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Preset timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Search timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 10. AF update timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 11. Jump timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 12. Check timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 13. Load timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 14. End timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 15. Buffer/control serial bus sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 16. Registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 17. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 18. LQFP64 (10x10x1.4mm) exposed pad down mechanical data and package dimensions

(exposed pad size for D2 and E2: 4.5mm max.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

7/60

Functional block diagram

TDA7529

1

Functional block diagram

Figure 1.

Functional block diagram

IBOC

FM

DAGC

AGC

AM

2

IF 10.7MHz

MSB/LSB

AGC

2

FM

WX

2

AFHOLD

AFSAMPLE

I

Q

AF update

I2C

SPI

Bus

Interface

AGC

TV1

TV2

2

Supply

AM

I

Q

DIV :N

PLL

DIV

VCO

2

Fref

AC00038

8/60

TDA7529

Pins description

2

Pins description

Figure 2.

Pin connection

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

1

2

3

4

5

6

7

8

9

BALUN1

48

GNDIF

TCIF1

IFout1

IFout2

BIASD2

VDDdec

VCCBUS

MISO

BALUNdec

DAC2

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

DAC1

FMMIX1in

FMMIX1dec

FMAGC2/GP7

FMAGC1

FMMIX2in

FMMIX2dec

GNDRF1

MOSI

CLK

10

11

12

13

14

CS/AS

PS

AMAGC1

AMMIXdec

AMMIXin

BUSGND

VCCRO

XTALO

XTALI

MIXbiasdec

IFAGC1

15

16

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

AC00039

Table 2.

Pin #

Pin assignment

Pin Name

Description

1

2

3

4

5

6

7

8

9

BALUN1

BALUNdec

DAC2

active balun input 1

active balun input 2 (de coupling)

Tuning DAC 2 output

DAC1

Tuning DAC 1 output

FMMIX1in

FM mixer input – high gain stage = mode 1

FMMIX1dec FM mixer de couple

FMAGC2/GP7 FM AGC voltage output / alternative GP7 output

FMAGC1

FMMIX2in

FM PIN diode driver output

FM Mixer input – low gain stage = mode2

9/60

Pins description

Table 2.

TDA7529

Pin assignment (continued)

Pin Name

Pin #

Description

10

11

12

13

14

15

16

17

18

FMMIX2dec FM Mixer de couple

GNDRF1

AMAGC1

AMMIXdec

AMMIXin

GND RF1 section

AMAGC PIN diode driver output

AM mixer de couple

AM mixer input

MIXbiasdec Mixer bias de coupling

IFAGC1

IFAGC2

IFAMP gain control via IFAGC - LSB

IFAMP gain control via IFAGC - MSB

GPIO 4 / VDS input

GP4/VDS

AMAGC2 /

GP8

19

AMAGC voltage output / alternative GP8 output

AF state machine hold output

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

AFHOLD

AFSAMPLE AF state machine sample output

VCCRF1

VCOdec1

Vtune

Supply RF1 section

BIAS de couple for VCO

VCO tuning voltage

BIAS de couple for VCO

VCO Ground

VCOdec2

GNDVCO

LFLC

Loop filter low current output

Loop filter high current output

PLL Ground

LFHC

GNDPLL

VCCPLL

GP1

Supply PLL

GPIO 1

GNDRO

XTALI

Ground PLL digital part

Reference oscillator input

Reference oscillator output

Supply PLL digital part

BUSinterface Ground

Protocol Select

XTALO

VCCRO

BUSGND

PS

CS/AS

CLK

Chip select / Address select

SPI / I2C clodk

MOSI

SPIdata input / I2C Data

SPI Data Output

MISO

VCCBUS

VDDdec

Supply of BUSinterface

De couple of internal 3.3V (=3,3V + Vbe)

10/60

TDA7529

Pins description

Table 2.

Pin #

Pin assignment (continued)

Pin Name

Description

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

BIASD2

IFout2

IFout1

TCIF1

GNDIF

TCIF2

IFdec

De coupling for Biasing

Differential IF output 2

Differential IF output 1

time constant IF AGC for AM

ground IF section

time constant IF AGC for FM

De couple of IF amplifier

IF input 4

IFin4

VCCIF

IFin3

Supply IF section

IF input 3

BIASD1

IFin2

De coupling for Biasing

IF input 2

GP2

GPIO 2

IFin1

IF input 1

GP5

GPIO 5

GNDRF2

TCAM

TCFM

VCCRF2

Balunout1

Balunout2

GND RF2 section = active balun GND

AM AGC time constant

FM AGC time constant

Supply voltage RF2 section

Active balun output 2 = FM output

Active balun output 1 = AM output

11/60

Function description

TDA7529

3

Function description

3.1

IMR Mixer and active balun output

The IMR mixer has two FM inputs (referred as mode 1 / mode 2) and one AM input

selectable by software. The FM inputs differ by their gains, noise figures, IIP3 and maximum

signal handling capability. The mode 1 FM input (with the higher gain, lower IIP3 and lower

noise figure) is normally coupled with passive antenna input stages; the mode 2 FM input is

normally used for input stages featuring an external preamplifier.

There are two single ended outputs of the IMR mixer: Balunout1 has a 4 dB higher gain than

Balunout2. It is not recommended to use both outputs in parallel.

The Balun1 pin is the current mixer output over an internal resistor. The LC filter at Balun1

can be realized with a low cost SMD-coil (Q ~ 4).

3.2

FM RF-AGC

The FM AGC system is controlled by a peak detector, whose gain can be varied by the

keyed AGC. The latter function is meant to be controlled by a D/A converter in the back-end

part of the system.

The time constant of the FM RF-AGC is defined by an external capacitor connected to

TCFM and programmable internal currents. The currents can be selected independently for

AGC attack and decay. By this the ratio between the attack and the decay time can be

programmed between 0.4 and 250.

The FM RF-AGC has two output pins to drive one PIN diode attenuator and the external

preamplifier gain control.

The AGC outputs can be programmed to the following modes:

1. Positive current I=f(e): after reaching the AGC threshold voltage, the current output

delivers a current I=f(e) up to 15mA in a voltage range from 0.1V (@10µA sink current)

up to V -1.2V with a quasi-exponential characteristic referred to the voltage at TCFM.

CC

Figure 3.

Positive current diagram

Iout

15mA

f(e) current

V_TCFM

AC00040

2. Pos/neg current I = f(e): below the AGC threshold voltage the AGC output sinks a

constant current of -5 mA. When the RF input level crosses the AGC threshold voltage,

the current is reduced down to 0 mA with a quasi-logarithmic behavior. At half control

voltage the current becomes positive and reaches up to 15mA following an exponential

function.

12/60

TDA7529

Function description

Figure 4.

Positive/negative current diagram

Iout

15mA

f(e) current

1.65V

AC00041

3. Constant current mode: the output current can be set to 2 mA source current. The AGC

detector is in power -down mode and only the PIN diode driver is active.

4. Voltage and current mode with hand-over: the Vthr level is programmable with 6 bit in

the range of 0.2V to 2.56V. The voltage Vthr is the internal reference voltage of an

external cascode transistor emitter feedback loop.

Figure 5.

Voltage and current mode with hand-over

Iout

Vout

Vthr

AC00042

The voltage output swing is comprised between 0V and 3.3V (VDD).

The microcontroller can read the voltage at the AGC capacitor via the serial control

interface.

3.3

AM RF-AGC

The AM AGC system is controlled by an average detector. The time constant of the AM RF-

AGC is defined by an external capacitor connected to TCAM and programmable internal

currents with symmetrical attack/decay behavior.

The AM RF-AGC has two output pins to drive one PIN diode attenuator and the external

preamplifier gain control.

The AGC outputs can be programmed to the same modes as the FM RF-AGC with the

exception of pos/neg current.

The microcontroller can read the voltage at the AGC capacitor via the serial control

interface.

13/60

Function description

TDA7529

3.4

IF AGC and IF amplifier

The IF AGC system is controlled in AM with an average detector and in FM with a peak

detector, and reduces the mixer gain. The time constant is defined by two external

capacitors connected to TCIF1 and TCIF2 respectively, and programmable internal

currents.

The microcontroller can read the voltage at the AGC capacitors via the serial control

interface.

The IF amplifier gain is not affected by the on-chip IF-AGC but is meant to be controlled by

the back-end part of the system through pins IFAGC1 and IFAGC2. The gain is reduced in 6

dB steps starting from the programmed value "G" according to the following table:

Table 3.

IF AGC and IF amplifier

IFAGC2

IFAGC1

Gain

0

1

0

1

0

G

G - 6dB

G - 12dB

G - 18dB

3.5

3.6

Dividers

The mixer divider V is followed by a divide-by-4-stage that generates 0°/90°/-90° LO signals

for the IMR mixer (90°/-90° mode to switch between upper or lower side-band suppression

in the IMR mixer).

The main divider N can be operated in integer mode.

D/A Converters

The front-end contains two D/A-converters for tuning the filters of the FM pre-stage. The

converters have a resolution of 9 bit.

14/60

TDA7529

Function description

3.7

VCO

The 3.7 GHz VCO has an internal switch that allows extending the oscillation frequency

range. This is required by the fact that each of the two resulting VCO sub-bands

(upper/lower) cannot individually cover the complete required frequency range versus

temperature and process; for this reason a calibration procedure is needed to determine the

process type (typical, slow, fast) and select the transition frequency between the two VCO

sub-bands.

To run the procedure the VCO range 2 must be selected, the synthesized frequency needs

to be set to 4GHz; then if Vtuning > 2.6V then the process is 'slow', if Vtuning < 1.7V then is

'fast' and otherwise is 'typical'. The switching frequency as a function of the process is

reported in the following table:

Table 4.

Switching frequency as a function of the process

SLOW

TYP

FAST

3.635GHz

3.72GHz

3.794GHz

3.8

3.9

FREF

The reference frequency for the PLL can be derived by a XTAL directly connected to the

device or by means of an LVDS signal. In the latter case an external matching resistor must

be used to obtain the desired input signal level.

A/D converter

The front-end contains a 6 bit SAR A/D-converter for sensing several analog values of the

tuner. The following analog sources can be switched to the ADC input by software

command:

●

FM RF AGC capacitor voltage

AM RF AGC capacitor voltage

IF AGC capacitor voltage (automatically connected to the FM or AM IF AGC filtering

capacitor)

●

PLL tuning voltage

Temperature sensor

GPIO 1 voltage

GPIO 2 voltage

ADC reference generated from VCC.

The ADC can be clocked by an integrated RC-oscillator, in which case the oscillation

frequency is programmable, or by the PLL reference frequency.

15/60

Function description

TDA7529

3.10

GPIO - general purpose IO interface pins

The front-end has seven GPIO - general purpose control pins to switch external stages

(output), e.g amplifiers, or to read the status of external stages (input), e.g. control voltages.

Some control pins are multiplexed with other functions that are not necessary in every tuner

design (FM AGC keying, AM cascode control). All the GPIOs may put in tristate or in enable

mode. When in enable the GPIOs can be configured as shown in the following table.

All GPIOs are short-circuit protected by current limiter and voltage-tolerant up to 3.5V.

Table 5.

GPIO - general purpose IO interface pins

GPIO ports

FUNCTION

selects function of GPIO1: if input, connects

GPIO1 to ADC (ADC must then be configured - AnlgIn to AD

to use GPIO1 as input); if output, level depends - DigOut

on GPIO Out Lev Ctrl → GPIO1

GPIO1

selects function of GPIO2: if input, connects

GPIO2 to ADC (ADC must then be configured

to use GPIO2 as input) and to KAGC (FM

KAGC must then be enabled); if output, level

depends on GPIO Out Lev Ctr → GPIO2

- AnlgIn to AD – Kagc In

- DigOut

GPIO2

GPIO4

selects function of GPIO4: if input, configures

GPIO4 as AM Cascode V_DSinput; if output,

level depends on GPIO Out Lev Ctrl → GPIO4

- AnlgIn

- DigOut

selects function of GPIO5: if input, it is directly

connected to read-only register byte 48 bit 4; if

output, level depends on GPIO Out Lev Ctrl →

GPIO5.

- DigIn

- Out (Dig or Anlg)

GPIO5

When set to input, it is necessary to set IF AMP

→ GPIO5 out mode to “ON GPIO5 out En”

(labels are wrong).

Also used for production testing as analog

output (not relevant for application).

selects function of GPIO6 if device is

configured in I²C mode: if input, it is directly

connected to read-only register byte 48 bit 5; if

output, level depends on GPIO Out Lev Ctrl →

GPIO5.

- Din (spi MISO out)

- Dout (spi MISO out)

GPIO6

When the device is configured in SPI mode,

program GPIO Out Lev Ctr → GPIO5 to “Low”.

The value of GPIO mode → GPIO5 does not

matter

selects function of GPIO7: if digital output is

selected, level depends on GPIO Out Lev Ctrl

→ GPIO7; otherwise, configures GPIO7 as FM - FM agc Vout

- Digital Out

GPIO7

GPIO8

AGC Vout

selects function of GPIO8: if output, level

- Digital Out

depends on GPIO Out Lev Ctrl → GPIO8;

- AM agc Vout

otherwise, configures GPIO8 as AM AGC Vout

16/60

TDA7529

Function description

3.11

AFSAMPLE/AFHOLD

On the TDA7529 there are two dedicated open drain pins (AFSAMPLE and AFHOLD), that

allow the control of the DSP (mute and quality controls) during AF update.

Details are given in Chapter 5.

3.12

Serial BUS interface

The TDA7529 has a serial data port for communication with the microcontroller. It is used for

programming the device and for reading out its detectors. This port supports data

2

communication using the SPI and the I C protocol. The data transfer of several consecutive

bytes is supported by the auto increment feature.

2

Table 6.

Supports data communication using the SPI and the I C protocol

SPI signal

I²C signal

Signal 1

PS

CS

Protocol Select SPI/I²C

Chip Select

PS

AS

Protocol Select SPI/I²C

Address Select

Clock

Signal 2

Signal 3

Signal 4

Signal 5

CLK

MOSI

MISO

Clock

CLK

DATA

GP6

Master Out – Slave In

Master In – Slave Out

bidirectional Data

General Purpose Out

The "PS"- pin (Protocol Select) determines which communication protocol is used. The

information is not latched, so any level change at this pin immediately affects the protocol

used by the TDA7529.

2

The SPI protocol is selected by setting PS = 0 while, during the I C operation, PS needs to

be open (internally set to 1).

SPI-Protocol: CPOL=1, CPHA=1.

The CS pin performs the Chip Select function during the SPI operation; it has to be reset to

0 during transmission or reception, otherwise set to 1 (the CS pin is set to 1 by leaving it

open).

Both the CS and the AS functions are performed by the CS pin.

2

When the I C mode is used, the "AS" pin determines which I C address or group of

addresses (see below) is used. Three different external connections are defined to

represent three groups of addresses (refer to the following table for details). The information

is not latched, so any level change at this pin immediately affects the address used by the

TDA7529.

First the IC address is transmitted including the R/W bit for setting the direction of the

following data transfer

17/60

Function description

Table 7.

TDA7529

2

I C addresses

Tuner:

Tuner 3

2.2V – 3.5V

1100 1xxd

Tuner 2

1.1V – 1.7V

1100 x1xd

Tuner 1

level at pin AS

address:

0.0V – 0.6V

1100 xx1d

MSB ... LSB

1100 000d

1100 001d

1100 010d

1100 011d

1100 100d

1100 101d

1100 110d

1100 111d

R / W

W

R / W

W

R / W

W

x

= must be "0" for reading, can be "1" or "0" for writing to the TDA7529

= determinates the direction of data transfer, reading or writing

d

R / W = indicates the address to read to and/or to write from a single TDA7529

W

= indicates those addresses that can be used to transmit equal data to several TDA7529 frontends. A

read out has no purpose for these addresses (data collision), but must be possible without damaging

the tuner IC.

2

The two serial bus protocols, I C and SPI, are as follows:

2

Figure 6.

I C (sub address mode)

1st byte

2nd byte

3rd byte

4th byte

7

1

0

R/W

7

SM

1

0

x

7

0

7

0

address

subaddress N

data byte N

data byte N+1

AC00043

Figure 7.

SPI

1st byte

2nd byte

3rd byte

4th byte

7

1

0

7

0

7

0

7

0

SM

subaddress N

R/W

data byte N

data byte N+1

data byte N+2

AC00044

Data auto increment mode is always active regardless of the serial bus mode chosen.

18/60

TDA7529

Electrical specifications

4

Electrical specifications

Electrical parameters are guaranteed if F = 100kHz, with frequency stability of +/- 20ppm

ref

max.

4.1

Absolute maximum ratings

Table 8.

Symbol

Absolute maximum ratings

Parameter

Test Condition

Min

Typ

Max

Units

V_CC

T_amb

T_stg

T_j

Abs. supply voltage

5.5

105

150

V

Ambient temperature range

Storage temperature

Junction temperature

-40

-55

°C

4.2

Thermal data

Table 9.

Symbol

Thermal data

Parameter

Test Condition, Comments

Min

Typ

Max

Units

2s2p std Jedec board with

thermal via underneath the

Thermal resistance junction to component (36 board via:

R_thj-amb

33

°C/W

ambient

diameter = 0.5mm / pitch =

1.5mm), max 30% missing

soldering

4.3

General key parameters

Table 10. General key parameters

Symbol

Parameter

Test Condition, Comments

Min

Typ

Max

Units

V_CC

I_CC

5V supply voltage

4.7

5

5.35

175

V

Supply current @ 5V

145

mA

Supply current @ 5V in power

down mode

I_{CC_pwd}

T_amb

9

14

mA

°C

Ambient temperature range

-40

105

19/60

Electrical specifications

TDA7529

4.4

FM - section

Refer to application circuit in figure 3. V = 4.7V to 5.35V; T

= -40 to +105°C; f = 76 to

c

CC

amb

108 MHz; 60dBµV antenna level; mono signal, unless otherwise specified. Antenna level

equivalence: 0dBµV = 1µV , all RF levels are intended as PD.

rms

Table 11. FM - section

Symbol

Parameter

Test Condition, Comments

Min

Typ

Max

Units

FM IMR Mixer and active balun

mode 1 (unloaded)

mode 2 (unloaded)

controlled by IF-AGC

mode 1

20

14

18

30

5

22

16

20

50

6.5

20

24

18

G_mix1

Mixer conversion gain

Gain attenuation range

Input impedance

dB

kΩ

R_in

mode 2

9.5

30

R_out

Output impedance

Max. output voltage

active balun

15

122

Ω

V_{out_max}

without clipping (unloaded)

dBµV

Mode1, Rsource=1.5kΩ,

noiseless

3

3.7

6

v_noise

Input noise voltage

nV/√Hz

Mode 2, Rsource=800,

noiseless

5

mode 1

123

132

125

134

up to Vin/tone = 90 dBµV

mode 2

IIP3

IIP2

3

^rdorder intercept point⁽¹⁾

^ndorder intercept point

dBµV

up to Vin/tone = 98 dBµV

mode 1

mode 2

144

152

2

dBµV

dB

without gain/phase adjust

with gain/phase adjust

30

40

IRR

Image rejection ratio

45

FM RF AGC

mode 1, min. setting

mode 1, max setting

mode 2, min. setting

mode 2, max setting

4 bit control

82

97

85

100

93

88

103

96

Mixer input referred

RF level threshold

L_thr

dBµV

90

105

0.5

108

1

111

1.5

Threshold steps

dB

AGC control pin 1

Logarithmic current

Pin diode source current

10

mA

AGC control pin 1

Logarithmic current

Pin diode sink current

-3

mA

Pin diode source current in

constant current mode

1

2

mA

Threshold shift keyed AGC

Control input = 1V

10.5

12.5

13.5

dB/V

1. parameter guaranteed by correlation.

20/60

TDA7529

Electrical specifications

4.5

AM - section

Refer to application circuit in figure 3. V = 4.7V to 5.35V; T

= -40 to +105°C; LW, MW

CC

amb

and SW bands; 74dBµV antenna level, unless otherwise specified. Antenna level

equivalence: 0dBµV = 1µVrms, all RF levels are intended as EMF.

Table 12. AM - section

Symbol

Parameter

Test Condition, Comments

Min

Typ

Max

Units

AM IMR Mixer and active balun

Gmix1

Δgmix1

Rin

Mixer conversion gain

Gain attenuation range

Input impedance

7.2

18

9

10.5

dB

controlled by IF-AGC

20

6.5

20

5

9.5

30

kΩ

Rout

Output impedance

Min. external load

15

W

400

122

W

Vin_max Max. output voltage

without clipping (unloaded)

dBµV

nV/√Hz

dBµV

dB

Vnoise

IIP3

Input noise voltage

^rdorder intercept point

6

8.3

3

130

159

30

134

IIP2

2^ndorder intercept point

Image rejection ratio

IRR

without gain/phase adjust

with gain/phase adjust

IRR

40

45

dB

AM RF AGC

External capacitance for time constant from 1nF to 4700nF – time constant values are directly proportional to the

external capacitor value

Lthr

min. setting

max setting

4 bit control

83

98

86

101

1

89

104

1.5

Mixer input referred

RF level threshold

dBµV

threshold steps

0.5

dB

AGC control pin 1

Logarithmic current

Pin diode source current

10

mA

AGC control pin 1 with 5µA

sink current

Min. voltage

Isink

0.1

V

5µA sink current

5

1

10

µA

mA

Pin diode source current in

constant current mode

V_CC

1.4

-

Max. voltage

AGC control pin 1

V_CC-1.2

V

Max. output voltage in GPO

mode

V_DD

0.3

AGC control pin 2

V_DD

0.3

V

Min. output voltage

21/60

Electrical specifications

TDA7529

Table 12. AM - section (continued)

Symbol

Parameter

Test Condition, Comments

Min

Typ

Max

Units

active in case of overdrive

(more than 7dB)

Fast attack time constant

0.05

0.5

5

ms

0.5-50

Range, mode T1

Range, mode T2

Range, mode T3

ms

2.5-250

Time constant

12.5-

1250

4.6

IF - section

Table 13. IF - section

Symbol

Parameter

Test Condition, Comments

Min

Typ

Max

Units

IF AMPLIFIER

Input 1-3 (FM,HD,AM), min.

Input 1-3 (FM,HD,AM), max

Input 4 (HD-Radio AM), min.

Input 4 (HD-Radio AM), max

3 bit control

23

36

25

38

17

31

2

27

40

Grange

Gain range

dB

15

19

29

33

Gstep

Gain step

1.5

16.5

5.2

230

2.5

19

dB

AGC range

18

6

ΔAGC

AGC steps

2-bit control

6.6

450

Rin_input1

Rin_input2

Rin_input3

Rin_input4

Input impedance input 1

FM –input @ 10.7MHz

330

W

HD-Radio FM input @

10.7MHz

Input impedance input 2

Input impedance input 3

Input impedance input 4

2.2

7

2.9

8.2

8.7

3.6

10

11

kΩ

AM input @ 10.7MHz

HD-Radio AM input @

10.7MHz

7

Differential output

impedance

Rout

15

W

Vout_max

Max. output voltage

115

117

0.5

dBµV

10pF between each IFAMP

outputs and GND, 10kΩ

differential load

Gain variation in loaded

conditions

Gain, load

IIP3,load

dB

10pF between each IFAMP

outputs and GND, 10kΩ

differential load

IIP3 decrease in loaded

conditions

1

input stage 1-3, @ 25dB gain

input stage 4, @ 17dB gain

input stage 1-3

119

130

142

154

122

133

IIP3

IIP2

3

^rdorder intercept point

dBµV

2^ndorder intercept point

input stage 4

22/60

TDA7529

Electrical specifications

Table 13. IF - section (continued)

Symbol

Parameter

Test Condition, Comments

Min

Typ

Max

Units

@ source impedance 330Ω ·

noiseless, @31dB gain

Vnoise_input 1 IN1 input noise voltage

Vnoise_input 2 IN2 input noise voltage

3.5

4.2

nV/√Hz

@ source impedance 470Ω ·

noiseless, @ 31dB gain, with

external 560Ω input

3.8

5

4.6

6.5

8.5

nV/√Hz

termination resistor

@ source impedance 2.2kΩ ·

noiseless, @ 29dB gain, with

external 2.7kΩ input

Vnoise_input 3 IN3 input noise voltage

termination resistor

@ source impedance 2.2kΩ ·

noiseless, @ 24dB gain, with

external 2.7kΩ input

Vnoise_input 4 IN4 input noise voltage

7

termination resistor

IF AGC

External capacitance for time constant from 10nF to 500nF in FM (asym. mode), from 100nF to 4700nF in AM (sym. mode)

– time constant values are directly proportional to the external capacitor value

FM, min. setting

FM, max setting

AM, min. setting

AM, max setting

88.5

99.5

86.5

96.5

1

91

101

89

93.5

103.5

91.5

101.5

2

Lthr

IFAmp input referred

Threshold steps

dBµV

99

1.5

dB

ms

Fast attack mode in AM-

mode, range

active in case of overdrive

0.05

0.5

5

FM: asym. mode U1

FM: asym. mode U2

AM: sym. mode S1

AM: sym. mode S2

10-500

0.05-2.5

2.0-100

20-1000

µs

ms

Time constant attack,

range

FM: asym. mode U1 / U2

AM: sym. mode S1

2-100

ms

Time constant decay,

range

AM: sym. mode S2

20-1000

23/60

Electrical specifications

TDA7529

4.7

VCO

Table 14. VCO

Symbol

Parameter

Test Condition, Comments

Min

Typ

Max

Units

Frequency range VCO

8% tuning range

3430

4010

MHz

Free running VCO; values

referred @ 100MHz

@ 10 Hz

@ 100 Hz

@ 1 kHz

@ 10 kHz

-40

-60

Phase Noise of LO

dBc/Hz

Hz

-46

-76

-86

-103

-106

FM reception, de-emphasis

50µs, fNF=20Hz...20kHz @

min. VCO frequency

Deviation error

8

4.8

Reference frequency input buffer

Table 15. Reference frequency input buffer

Symbol

Parameter

Test Condition, Comments

Min

Typ

Max

Units

Reference frequency input buffer mode

Max input voltage high

Min. input voltage low

1475

400

mV

925

200

150

10

Input differential voltage

Input impedance (xtal mode)

Input impedance (lvds mode)

Input voltage range

mV

kΩ

Single ended mode

200

1000

mV_PP

4.9

Dividers

Table 16. Dividers

Symbol

Parameter

Test Condition, Comments

Min

Typ

Max

Units

Mixer divider V – integer values

N_Vdivider value divider_V

7 bit

5

131

0.5

Divide by 4 – generation of 0°/90°/-90° LO signal for IMR

I/Q phase error of divider

phase calibration in IMR

-0.5

992

1

DEG

Main divider N – integer divider

N_N

Reference divider R – integer values

N_Rdivider value divider_R

divider value divider_N

21bit (32/33 pre scaler)

8 bit

2097151

255

24/60

TDA7529

Electrical specifications

4.10

Phase locked loop

Table 17. Phase Locked Loop

Symbol

Parameter

Test Condition, Comments

Min

Typ

Max

Units

Δf < 0,01%

@ f_PFD= 100 kHz

Settling time AM/FM

Spurious suppression

800

1200

µs

@ divided VCO signal

70

dB

4.11

Phase frequency detector and charge pump

Table 18. Phase frequency detector and charge pump

Symbol

Parameter

Test Condition, Comments

Min

Typ

Max

Units

PFD

f_PFD

PFD input frequency

2

3000

kHz

Charge pump

high current mode bit1

high current mode bit2

high current mode bit3

high current mode bit4

low current mode bit5

low current mode bit6

low current mode bit7

low current mode bit8

low current mode bit9

-0.4

-0.8

-1.7

-3.1

-40

-0.65

-1.3

-2.4

-4.5

-60

-0.9

-1.7

mA

µA

-3.1

-5.8

Sink current

-80

-120

-240

-480

-960

-160

-320

-640

-1280

µA

-160

-320

-640

µA

high current mode bit1

high current mode bit2

high current mode bit3

high current mode bit4

low current mode bit5

low current mode bit6

low current mode bit7

low current mode bit8

low current mode bit9

0.4

0.8

1.7

3.1

40

0.65

1.3

0.9

1.7

mA

µA

2.4

3.1

4.5

5.8

Source current

60

80

120

240

480

960

160

320

640

1280

µA

160

320

640

µA

25/60

Electrical specifications

TDA7529

4.12

Temperature sensor

Table 19. Temperature sensor

Symbol

Parameter

Test Condition, Comments

Min

Typ

Max

Units

Temperature range

-40

150

°C

°C/LSB (no direct

measurement possible)

Resolution

5

°C

Absolute error

Relative error

15

°C

0.5

LSB

4.13

D/A-Converter

Table 20. D/A-Converter

Symbol

Parameter

Test Condition, Comments

Min

Typ

Max

Units

Output voltage minimum value Unloaded output

0.5

0.6

0.8

V

V_out

Output voltage maximum

Unloaded output

value

VCC –

0.2

VCC –

0.1

V

Output impedance

Max. output current

2

kΩ

µA

500

8.5

-2

Average Voltage step

resolution 9bit

@ C_L=1nF

9

9.5

2

mV

LSB

µs

INL

DNL

-0.5

0.5

40

Conversion time

20

Supply voltage ripple rejection

ratio

VSRR

20

dB

4.14

A/D-Converter

Table 21. A/D-Converter

Symbol

Parameter

Test Condition, Comments

Min

Typ

Max

Units

INL

-2

-0.5

0

2

0.5

V_DD

7

LSB

V

DNL

Input voltage range

Conversion time

t_ADC

µs

26/60

TDA7529

Electrical specifications

4.15

GPIO – general purpose IO interface pins

Table 22. GPIO - general purpose IO interface pins

GPIO functionality

Multiplexed

GPIO-Output

Pin name

GPIO-Input

functionality details

are given in the

corresponding

High level

Low level

Functionality

voltage

chapters

Source

Sink

current

voltage

current

GP1

GP2

GP4

GP5

GP6

GP7

GP8

3.3V

1 mA

0.1 mA

1 mA

0V

1 mA Analog input ADC

10 mA AM cascode V_DSinput

1 mA Digital Input

1 mA

0 ... 3.3V

0 ... 3.3V FM key AGC input

0 ... 3.3V

0 / 3.3V

0 / 3.3V SPI MISO output

FM-AGC voltage output

AM-AGC voltage output

1 mA

Symbol

Parameter

Test Condition

Min

Typ

Max

Units

High level output voltage

Low level output voltage

@ 100kΩ load to GND

@ 100kΩ load to V_DD

V_DD-0.3

V

0.3

GP1 / GP2 / GP5 / GP6:

High level source current

low level sink current

0.5

1

mA

@ 1kΩ load to GND

GP4

0.08

0.1

@ 1kΩ load to GND

GP1 / GP2 / GP5 / GP6:

@ 1kΩ load to V_DD

0.8

1

mA

GP4:

@ 100Ω load to V_DD

8.0

100

0

10

mA

kΩ

V

Input impedance

digital input mode

GP1 / GP2

Input voltage range

3.5

GP5 / GP6 used as digital

input

High level input voltage

Low level input voltage

2.2

V

GP5 / GP6 used as digital

input

-0.05

1.0

4.16

AFSAMPLE / AFHOLD

Table 23. AFSAMPLE / AFHOLD

Symbol Parameter

Output voltage at

Test Condition, Comments

Min

Typ

Max

Units

3.6

V

AFSAMPLE/AFHOLD

Maximum sink current

V_o= 0.4V

800

μA

27/60

Electrical specifications

TDA7529

4.17

Serial Data Interface

Table 24. Serial Data Interface

Symbol

Parameter

Supply voltage

Test Condition, Comments

Min

Typ

Max

Units

VDD

2.7

3.5

V

Guaranteed range @ SPI

Guaranteed range @ I²C

4

1

MHz

f_clk

Clock frequency

Ready for communication

after Power-On-Reset

Power On Delay time

10

ms

High level output voltage

Low level output voltage

High level source current

low level sink current

Rise / fall time

Output signals

V_DD-0.3

-0.05

0.08

0.8

V_DD

0.3

V

Output signals

0.1

1

mA

ns

V

Output signals

Output signals, 90%

Input signals, except AS

AS input signal

15

25

40

3.5

1.0

3.5

1.7

0.6

High level input voltage

Low level input voltage

High level input voltage

2.0

-0.05

2.2

V

Medium level input voltage AS input signal

1.1

V

Low level input voltage

Input impedance

AS input signal

Input signals

All signals

-0.05

100

V

kΩ

Power-On impedance

100

Input signals except CLK, min.

acceptable duration range,

90%

0.01

1000

10

µs

Rise / fall time

Input signal CLK, min.

acceptable duration range,

90%

28/60

TDA7529

Tuning state machine

5

Tuning state machine

Frequency changes in a system employing the TDA7529 can be efficiently performed using

a built-in state machine which simplifies the microprocessor supervisory functions. The state

machine, which can work in 8 different modes, can be invoked by a simple WRITE operation

into the tuner registers and, provided that the frequency to be jumped to has been pre-

loaded into the front-end registers through a previous separate or is loaded through a

concurrent WRITE operation, the FE jump sequence is automatically managed and flags

are provided to the back-end to indicate the current condition.

5.1

Tuning state machine modes

Hereafter the description of the 8 modes can be found. They are chosen by Byte 12

bits<6:4>.

The diagrams depicting the FE and flag conditions for each of the 8 modes are as follows:

5.1.1

5.1.2

Mode 000: buffer (nil)

When this mode is selected, no action is undertaken by the state machine.

Mode 001: preset

Figure 8.

Preset timing diagram

bus

STOP

event

regs

swap

EVENTS

wait T_1ms

wait for T_plllock

wait T_60ms

TIME

transmission with subaddr. bit 7 = 1

wait 50 us

AFSAMPLE

AFHOLD

B.E. OPERATION

mute audio

quality dets in fast mode

unmute audio

AC00045

This mode is used to jump to a different frequency and stay there, with reception at the end

of the sequence.

AFSAMPLE can be used to tell the back-end when to mute and to unmute the audio output.

The 60 ms mute time (programmable) after the PLL has reached the locked condition can

be used to check the RDS signal presence and content in addition to the analog quality

information.

AFHOLD can be used to tell the back-end to switch to faster time constants for quick quality

acquisition.

29/60

Tuning state machine

TDA7529

5.1.3

Mode 010: search

Figure 9.

Search timing diagram

bus

STOP

event

regs

swap

EVENTS

wait T_1ms

wait for T_plllock

TIME

transmission with subaddr. bit 7 = 1

wait 50 us

AFSAMPLE

AFHOLD

B.E. OPERATION

mute audio

quality dets in fast mode

AC00046

This mode is used to jump to a different frequency and stay there, with audio muted.

AFSAMPLE can be used to tell the back-end when to mute the audio output.

AFHOLD can be used to tell the back-end to switch to faster time constants for quick quality

acquisition.

5.1.4

Mode 011: AF update

Figure 10. AF update timing diagram

bus

STOP

event

regs

swap

regs

swap

EVENTS

TIME

transmission with subaddr. bit 7 = 1

AFSAMPLE

AFHOLD

B.E. OPERATION

mute audio

hold

unmute audio

freeze

AF qual

AC00047

This mode is used to jump to an AF frequency, check its quality, jump back to the starting

frequency and continue reception.

AFSAMPLE can be used to tell the back-end when to acquire the AF frequency quality.

AFHOLD can be used to tell the back-end to mute/unmute the audio and keep normal

processing on hold.

30/60

TDA7529

Tuning state machine

5.1.5

Mode 100: jump

Figure 11. Jump timing diagram

bus

STOP

event

regs

swap

EVENTS

wait T_1ms

wait for T_plllock

wait T_0.5ms

TIME

transmission with subaddr. bit 7 = 1

wait 50 us

AFSAMPLE

AFHOLD

B.E. OPERATION

mute audio

hold

unmute audio

AC00048

This mode is used to jump to a different frequency and stay there, with reception at the end

of the sequence.

AFHOLD can be used to tell the back-end to mute/unmute the audio and keep normal

processing on hold.

AFSAMPLE can be used to tell the back-end when the quality signal processing can be

restarted, with a stable situation to start from.

5.2

Mode 100: check

Figure 12. Check timing diagram

bus

STOP

event

regs

swap

EVENTS

wait T_1ms

wait for T_plllock

TIME

transmission with subaddr. bit 7 = 1

AFSAMPLE

AFHOLD

B.E. OPERATION

mute audio

hold

AC00049

This mode is used to jump to a different frequency and stay there, with audio muted.

AFHOLD can be used to tell the back-end to mute/unmute the audio and keep normal

processing on hold.

AFSAMPLE can be used to tell the back-end when to freeze the quality signal processing.

31/60

Tuning state machine

TDA7529

5.3

Mode 110: load

Figure 13. Load timing diagram

bus

STOP

event

EVENTS

TIME

transmission with subaddr. bit 7 = 1

regs

swap

AC00050

The content of the buffer and control registers is swapped. No transition occurs on the

AFHOLD and AFSAMPLE lines.

5.4

Mode 111: end

Figure 14. End timing diagram

bus

STOP

EVENTS

event

TIME

transmission with subaddr. bit 7 = 1

wait 50 us

AFSAMPLE

AFHOLD

B.E. OPERATION

unmute audio

AC00051

This mode is used to end sequences that terminate with muted audio, after the decision on

whether to stay to that frequency or jump to a different one has been taken.

AFHOLD can be used to tell the back-end to unmute the audio.

AFSAMPLE can be used to tell the back-end to restore normal quality signal processing.

Most of the wait times of the algorithm can actually be programmed.

The following table summarizes the minimum, maximum and default values of the

programmable wait times. The indicated values are valid only for the advised configuration

where the phase detector reference frequency is 100 kHz.

32/60

TDA7529

Tuning state machine

Table 25. Values of the programmable wait times

PARAMETER NAME

REGISTER

VALUE

TIME

min.

00000

00110

20 us

1 ms

T_plllock

Byte 15 bits<7:3>

default

maximum

min.

11111

5 ms

000000

000101

111111

000000

001100

111111

000000

011000

111111

00000

70 us

0.5 ms

5 ms

T_0.5ms

Byte 30 bits<7:2>

Byte 20 bits<7:2>

Byte 29 bits<7:2>

Byte 04 bits<7:3>

default

maximum

min.

10 us

1 ms

T_1ms

default

maximum

min.

5 ms

50 us

2 ms

T_2ms

default

maximum

min.

5 ms

1 ms

T_60ms

default

maximum

10111

60 ms

80 ms

11111

5.5

Register SWAP

Some of these modes contain one or two register "swap" operation(s). The changes within

the register structure during a swap operation depend on the operating mode of the chip.

If the chip is programmed in the "buffer/control" mode (chosen by setting byte 12 bit 7 = 1),

which is necessary to take advantage of the tuning state machine, it is suggested that the

microprocessor write data only in the normal register bank (bytes from 16 to 31), because

the state machine itself takes care of exchanging the content of the normal register bank

with that of the shadow bank (bytes from 32 to 47) during a swap. The normal registers are

intended to be written to by the radio microprocessor, whereas the registers that actually

control the device circuits are the shadow ones.

In any case it is suggested that the bits 5 and 4 of byte 0, that define which control bank is

actually used to drive the device circuits, should not be touched after setting them to 0 after

reset because they are automatically updated by the tuning state machine.

33/60

Tuning state machine

TDA7529

5.6

State machine start

The tuning state machine is activated only at the end of the transmission if bit 7 of the

subaddress is 1. The activation sequence, therefore, is to be done in the following way.

Figure 15. Buffer/control serial bus sequence

ADDRESS

(if I2C)

START

SUBADDRESS

REGS 0:31

STOP

bit 7 = 1

REG 12 bit 6:4

sets desired state

machine mode

sets F2 into buffer

registers

tuning state

machine

starts

AC00052

34/60

TDA7529

Registers description

6

Registers description

Figure 16. Registers description

Power

No

name

r/w

MSB (7)

6

5

4

3

2

1

LSB (0)

on

default

00h

r/w

x

ShAGC

ADCs1

ShPLL

ADCs0

GPIOen

ADCautomode

GPIO2io

Mixout1

PWR

Temp_pwr

GPIO1io

Mixout2

0 Short reg

1 ADCctrl

2 GPIOval

3 AGCmixCtrl

4 Misc1

ADCen

ADCstart

ADCclk

ADCs2

RCenable

CP_curr_switch

GPO8_AMAGCv GPO7_FMAGCv

GPIO6_MISO

FMAGCpwr

WAIT60ms(2)

divr5

GPIO5_Aout

AMAGCpwr

WAIT60ms(1)

divr4

GPO4_AMcas

MixinFMAM

WAIT60ms(0)

divr3

00h

IFin1_AM_FM

WAIT60ms(4)

divr7

KeyAGCen

WAIT60ms(3)

divr6

BalunoutIMP

disvcc

00h

PLLtest

AMAGC_Isink

divr0

00h

5 DivR

divr2

divr1

00h

6 IFAGC_SH

7 FMAGC

IFAGC_FM_AM

FMthr3

IFAGCthr2

FMthr2

IFAGCthr1

FMthr1

IFAGCthr0

FMthr0

GPIO5 output

FMAGCmodeV1

Vthr1

IFsection_pwr

FMAGCmodeV0

Vthr0

00h

FMAGCmodeC1

Vthr3

FMAGCmodeC0

Vthr2

00h

AMAGCfat

IFAMP_Ictrl2

IMRph3

AFH_MUX

IFAMP_Ictrl1

IMRph2

Vthr5

Vthr4

00h

8 FM_AM_Vthr

9 MIXalign1

IMRF2

IMRF1

IMRF0

00h

IredH

IMRph1

IredL

IMRph0

Casc_ctrl

IMRG3

10 MIXalign2

11 PLLctrl

IMRG2

SWfref

IMRG1

IMRG0

00h

DZ3

DZ2

DZ1

MODE0

CPcur_800u

DS4

divRen

PLLpwr

00h

DZ4

FUNC

12 PLLctrl2

13 PLLtest

14 Misc2

MODE2

MODE1

PFD_D0

reg48sel

DS3

DS2

DS1

00h

PFD_D1

PLLT4

PLLT3

PLLT2

PLLT1

PLLT0

00h

POL

IFAGCin4ctrl

WAIT LOCK(4)

IFAGCtcAM

AMthr3

EnSMOOTH

IFAMP_Ictrl0

VCOMag1

VCOMag0

00h

RCfreq_1

WAIT LOCK(0)

FMtc3

RCfreq_0

DIVVtest

15 WAIT_LOCK

16 AGCtc_A

17 AMAGC_A

18 GPIOm_A

19 IFCTRL_A

20

00h

WAIT LOCK(3)

IFAGCtcFM

AMthr2

WAIT LOCK(2)

AMtc1

WAIT LOCK(1)

AMtc0

VCOext

FMtc1

LOCK_bit

FMtc0

FMtc2

00h

AMthr1

AMthr0

AMAGCmodeC1

GPO4hl

AMAGCmodeC0

AMAGCmodeV1 AMAGCmodeV0

GPO8hl

GPO7hl

GPIO6hl

IFAmpgainA1

WAIT1ms(3)

divnA18

GPIO5hl

IFAmpgainA0

WAIT1ms(2)

divnA17

GPIO2hl

RCtest

GPIO1hl

IFin0_Std_IBOC

WAIT1ms(5)

divnA20

IFAmpgainA2

WAIT1ms(4)

divnA19

MixinFM

AMAGCinbuffer

WAIT1ms(0)

divnA15

WAIT1ms(1)

divnA16

21 DivN_A1

22 DivN_A2

23 DivN_A3

24 DivV_A

25 CPcur_A

26 DAC1_A

27 DAC2_A

28 PLL_DAC_A

29 Misc4_A

30

divnA14

divnA6

divnA13

divnA5

divnA12

divnA11

divnA10

divnA9

divnA8

divnA7

divnA4

divnA3

divnA2

divnA1

divnA0

VCO1r

divVA6

divVA5

divVA4

divVA3

divVA2

CPAl2

divVA1

CPAl1

divVA0

CPAl0

CPAh3

CPAh2

CPAh1

CPAh0

CPAl3

DAC1A8

DAC1A6

DAC1A5

DAC2A5

DAC1A4

DAC2A4

DAC1A3

DAC1A2

DAC1A1

DAC2A1

DAC2off

DAC1A1

DAC2A1

DAC1off

MIN16

DAC2A8

DAC2A6

DAC2A3

DAC2A2

IQselA

VCOsw

DAC2A0

DAC1A0

WAIT2ms(5)

WAIT0.5ms(5)

WAIT2ms(4)

WAIT0.5ms(4)

WAIT2ms(3)

WAIT2ms(2)

WAIT2ms(1)

WAIT0.5ms(1)

WAIT2ms(0)

WAIT0.5ms(0)

WAIT0.5ms(3)

WAIT0.5ms(2)

AGCtest1

ADCDAC1

AGCtest0

31

IF test

ADC test

ADCDAC5

ADCDAC4

ADCDAC3

ADCDAC2

ADCDAC0

32 AGCtc_B

33 AMAGC_B

34 GPIOm_B

35 IFCTRL_B

36 AMFilt_B

37 DivN_B1

38 DivN_B2

39 DivN_B3

40 DivV_B

41 CPcur_B

42 DAC1_B

43 DAC2_B

44 PLL_DAC_B

45 Misc4_B

46

this byte is valid on the output if bit SHAGC is set to '1', otherwise byte Nr. 16 is valid on the output

all bytes from 33 to 45 are valid on the output if SHPLL is set to '1', otherwise byte 17 to 29 are valid on the output

47

48 READ_Status

49 READ_ADC

r

lock

GPIO6r

ADC5

GPIO5r

ADC4

MaskMetal1

ADC3

MaskMetal0

ADC2

MaskSet1

ADC1

MaskSet0

ADC0

ADCok

35/60

Registers description

TDA7529

6.1

Data byte specification

6.1.1

Short_reg (0)

Table 26. Short_reg (0)

MSB

LSB

D₀

Function

D₇

D₆

D₅

D₄

D₃

D₂

D₁

Global PWR

0

1

Power down the IC

Power on the IC

GPIO enable

0

1

all GPIO in tristate

all GPIO enable

ADCen

0

1

6bit ADC on

6bit ADC off

ADCstart

0

1

No conversion

Starts a single AD conversion

ShPLL

0

1

PLL register from 17 to 31 are valid

PLL register from 33 to 47 are valid

ShAGC

AGC TC register 16 is valid

AGC TC register 32 is valid

0

1

X

Not used

X

36/60

TDA7529

Registers description

6.1.2

ADCctrl (1)

Table 27. ADCctrl (1)

MSB

LSB

D₀

Function

D₇

D₆

D₅

D₄

D₃

D₂

D₁

Temperature sensor power

0

1

Enabled

Disabled

ADC auto mode

0

1

automatic restart disable

automatic restart enable

RC oscillator enable

enable

disable

0

1

X

ADCstart (like bit 0.3)

ADC input selection

Temp sensor

FM AGC

0

1

0

1

0

1

0

1

0

1

0

1

0

1

AM AGC

IF AGC

VCO tuning voltage (3/5 * Vtune)

GP1

GP2

2/5 * VCC

ADC clock selection

0

1

ADC clock source = RC osc

ADC clock source = refdiv output

37/60

Registers description

TDA7529

6.1.3

GPIO mode (2)

Table 28. GPIO mode (2)

MSB

LSB

D₀

Function

D₇

D₆

D₅

D₄

D₃

D₂

D₁

GPIO1 input / output

0

1

Analog input to AD converter

digital output

GPIO2 input / output

Analog input to AD converter

Digital output

0

1

CP Current Switch

0

1

Automatic switch disabled

Automatic switch enabled

GPIO4 input / output

0

1

Analog Input

digital output

GPIO5 input / output

digital input

output (analog or digital)

0

1

GPIO6 input / output

0

1

digital input (or MISO output in SPI mode)

digital output (or MISO output in SPI mode)

GPIO7 input / output

FM AGC voltage output

Digital output

0

1

GPIO8 input / output

AM AGC voltage output

Digital output

0

1

38/60

TDA7529

Registers description

6.1.4

AGC and mixer control (3)

Table 29. AGC and mixer control (3

MSB

LSB

D₀

Function

D₇

D₆

D₅

D₄

D₃

D₂

D₁

Mixout 1 / 2

0

1

0

1

0

1

All Off = power down mixer section

Mixout 1 active

Mixout 2 active

Forbidden state

Balun output drive capability

Low drive capability

0

1

High drive capability

Mixer input FM / AM selection

AM input active

0

1

FM input active

AM AGC On / Off

0

1

Off

On

FM AGC On / Off

Off

0

1

On

Keyed AGC enable

0

1

Keyed AGC off

keyed AGC on

IF input selection FM / AM

IF input AM

0

1

IF input FM

39/60

Registers description

TDA7529

6.1.5

Register (4)

Table 30. Register (4)

MSB

LSB

D₀

Function

D₇

D₆

D₅

D₄

D₃

D₂

D₁

AMAGC Isink (2mA fixed current)

0

1

Off

On

PLLtest

Off

0

1

On

Disvcc

0

1

POR activated from IFVCC

POR non activated from IFVCC

WAIT60ms

0

1

0

1

0

1

0

1

0

1

1ms (min. value)

60ms (default value)

80ms (max value)

6.1.6

Divider R (5)

Table 31. Divider R (5)

MSB

LSB

D₀

Divider R value

D₇

D₆

D₅

D₄

D₃

D₂

D₁

Divider R value

X

DivR0

:

X

DivR7

40/60

TDA7529

Registers description

6.1.7

IF AGC control (6)

Table 32. IF AGC control (6)

MSB

LSB

D₀

Function

D₇

D₆

D₅

D₄

D₃

D₂

D₁

IF section On / Off

0

1

Off

On

GPIO 5 output mode

0

1

Off

On = GPIO 5 analog output enable

X

Not used

IF AGC threshold

0

:

0

:

0

1

:

IF output level = 89dBµV(AM) / 91dBµV (FM)

IF output level = 90.5dBµV(AM) / 92.5dBµV (FM)

:

IF output level = 99dBµV(AM) / 101dBµV (FM)

1

IF AGC mode FM / AM selection

FM mode

0

1

AM mode

41/60

Registers description

TDA7529

6.1.8

FM AGC (7)

Table 33. FM AGC (7)

MSB

LSB

D₀

Function

D₇

D₆

D₅

D₄

D₃

D₂

D₁

Voltage output mode

0

1

0

1

0

1

Off

N/A

Calibration mode

Voltage output On

Current output mode

Off

0

1

0

1

0

1

Constant 2mA output

Positive current output

Neg. / Pos. current output

FM AGC threshold

Mixer input level = 93dBµV (FM1) / 97dBµV (FM2)

Mixer input level = 94dBµV (FM1) / 98dBµV (FM2)

Mixer input level = 95dBµV (FM1) / 99dBµV (FM2)

Mixer input level = 96dBµV (FM1) / 100dBµV (FM2)

Mixer input level = 97dBµV (FM1) / 101dBµV (FM2)

Mixer input level = 98dBµV (FM1) / 102dBµV (FM2)

Mixer input level = 99dBµV (FM1) / 103dBµV (FM2)

Mixer input level = 100dBµV (FM1) / 104dBµV (FM2)

Mixer input level = 93dBµV (FM1) / 97dBµV (FM2)

Mixer input level = 92dBµV (FM1) / 96dBµV (FM2)

Mixer input level = 91dBµV (FM1) / 95dBµV (FM2)

Mixer input level = 90dBµV (FM1) / 94dBµV (FM2)

Mixer input level = 89dBµV (FM1) / 93dBµV (FM2)

Mixer input level = 88dBµV (FM1) / 92dBµV (FM2)

Mixer input level = 87dBµV (FM1) / 91dBµV (FM2)

Mixer input level = 86dBµV (FM1) / 90dBµV (FM2)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

42/60

TDA7529

Registers description

6.1.9

AGC voltage threshold (8)

Table 34. AGC voltage threshold (8)

MSB

LSB

D₀

Function

D₇

D₆

D₅

D₄

D₃

D₂

D₁

Transfer voltage from voltage out to current out

0

:

0

:

0

:

0

:

0

:

0

1

:

200mV

237.5mV

:

0

1

2.5625V

2.6V

1

AM fast attack

0

1

Off

On

6.1.10

Mixer alignment 1 (9)

Table 35. Mixer alignment 1 (9)

MSB

LSB

D₀

Function

D₇

D₆

D₅

D₄

D₃

D₂

D₁

IQ-filter frequency adjust

0

:

0

:

0

1

:

+2.4MHz

+1.8MHz

:

0

1

:

0

:

0

:

-1.8MHz

1

Cascode control loop On / Off

0

1

On

Off

Mixers current control

Normal bias

0

1

0

1

0

1

Low reduction

High reduction

N/A

IFAMP driving capability

Normal

0

1

0

1

0

1

Intermediate 1

Intermediate 2

High

43/60

Registers description

TDA7529

6.1.11

Mixer alignment 2 (10)

Table 36. Mixer alignment 2 (10)

MSB

LSB

D₀

Function

D₇

D₆

D₅

D₄

D₃

D₂

D₁

IQ-filter gain adjust

0

:

1

:

1

0

:

1

0

1

:

-0.7dB

-0.6dB

-0.5dB

:

0

1

:

0

:

0

:

0

:

0dB

:

1

0

1

+0.6dB

+0.7dB

IQ-filter phase adjust

0

:

0

1

:

0

1

0

:

0

1

0

1

0

:

+0.2 deg

+0.4 deg

+0.6 deg

:

0

1

:

1

0

1

:

1

0

1

0

:

1

0

1

0

1

0

:

+1.2 deg

-1.2 deg

-1.0 deg

-0.8 deg

-0.6 deg

:

1

0

1

-0.2 deg

0

44/60

TDA7529

Registers description

6.1.12

PLL control 1 (11)

Table 37. PLL control 1 (11)

MSB

LSB

D₀

Function

D₇

D₆

D₅

D₄

D₃

D₂

D₁

PLL enable

PLL Off

0

1

PLL On

Divider R enable

Divider R off; = div / 1

0

1

Divider R on

Select reference input

Reference frequency input = LVDS

0

1

Reference frequency input = Xtal

Charge pump current 800μA

0 µA

0

1

800 µA

Slope of high current CP

0

:

0

:

0

:

0

:

highest

:

1

lowest

6.1.13

PLL control 2 (12)

Table 38. PLL control 2 (12)

MSB

LSB

D₀

Function

D₇

D₆

D₅

D₄

D₃

D₂

D₁

Delay of high current CP

shortest

0

:

0

:

0

:

0

:

longest

1

State machine modes decode

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Buffer mode

Preset

Search

AF update

Jump

Check

Load

End

Register functionality control

Normal/shadow mode

0

1

Buffer/control mode

45/60

Registers description

TDA7529

6.1.14

PLL test (13)

Table 39. PLL test (13)

MSB

LSB

D₀

Function

D₇

D₆

D₅

D₄

D₃

D₂

D₁

PLL test

X

1

0

Set to default

PFD

0

1

default

0

PFD polarity

6.1.15

Misc 2 (14)

Table 40. Misc 2 (14)

MSB

LSB

D₀

Function

D₇

D₆

D₅

D₄

D₃

D₂

D₁

VCO magnitude

0

1

0

1

0

1

1V

2V

3V

4V

Oscillation frequency of RC oscillator

0

1

0

1

0

1

0.68 MHz

1.31 MHz

1.92 MHz

2.49 MHz

IFAMP current control

Normal bias

0

1

High current mode bias

Reg48sel

0

1

ShAGC and ShPLL on D48<1:0>

MaskMetal and MaskSet on D48<1:0>

EnSMOOTH

0

1

Smooth disabled

Smooth enabled

IFAGC control when IN4 selected

Normal

0

1

Thresholds shift

46/60

TDA7529

Registers description

6.1.16

WAIT LOCK (15)

Table 41. WAIT LOCK (15)

MSB

LSB

D₀

Function

D₇

D₆

D₅

D₄

D₃

D₂

D₁

TEST

0

1

0

1

0

1

D18<0>

LOCK_bit

CMPout

VdivOUT

WAIT LOCK

0

1

0

1

0

1

0

1

0

1

0.04ms (min. value)

1ms (default value)

5.08ms (default value)

6.1.17

AGC time constant settings (16 / 32)

Table 42. AGC time constant settings (16 / 32)

MSB

D₇

LSB

D₀

Function

D₆

D₅

D₄

D₃

D₂

D₁

FM AGC decay time constant

0

1

0

1

0

D1

D2

D3

FM AGC attack time constant

0

1

0

1

0

A1

A2

A3

AM AGC time constant

0

1

0

1

0

T1

T2

T3

IF AGC time constant FM

0

1

U1

U2

IF AGC time constant AM

0

1

S1

S2

47/60

Registers description

TDA7529

6.1.18

AMAGC control (17 / 33)

Table 43. AMAGC control (17 / 33

MSB

LSB

D₀

Function

D₇

D₆

D₅

D₄

D₃

D₂

D₁

AM AGC voltage output mode

Off

0

1

0

1

0

1

Voltage output / sense internal

Calibration

Voltage output / sense external

AM AGC current output mode

0

1

0

1

0

1

Off

Constant 2mA

Positive current

N/A

AM AGC thresholds

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Mixer input level = 94 dBµV

Mixer input level = 95 dBµV

Mixer input level = 96 dBµV

Mixer input level = 97 dBµV

Mixer input level = 98 dBµV

Mixer input level = 99 dBµV

Mixer input level = 100 dBµV

Mixer input level = 101 dBµV

Mixer input level = 94 dBµV

Mixer input level = 93 dBµV

Mixer input level = 92 dBµV

Mixer input level = 91 dBµV

Mixer input level = 90 dBµV

Mixer input level = 89 dBµV

Mixer input level = 88 dBµV

Mixer input level = 87 dBµV

48/60

TDA7529

Registers description

6.1.19

GPIO output level control (18 / 34)

Table 44. GPIO output level control (18 / 34)

MSB

D₇

LSB

Function

D₆

D₅

D₄

D₃

D₂

D₁

D₀

GPIOx high / low output level

0

1

GPIO1 low

GPIO1 high

GPIO2 low

GPIO2 high

:

0

1

:

X

:

X

:

X

:

X

:

X

:

GPIOx low / high

:

GPIO8 low

GPIO8 high

0

1

6.1.20

IF control (19 / 35)

Table 45. IF control (19 / 35)

MSB

LSB

Function

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

X

Not used

RC test

0

1

Test enabled

Test disabled

AMAGC input buffer

Buffer enabled

0

1

Buffer disabled

Mixer input selection for FM

FM1 mixer input

0

1

FM2 mixer input

IF amplifier Gain

0

:

0

:

0

1

:

25dB (input1-3) / 19dB (input4)

27dB (input1-3) / 21dB (input4)

:

1

0

1

37dB (input1-3) / 31dB (input4)

39dB (input1-3) / 33dB (input4)

IF input selection analog / IBOC

0

1

IBOC

Analog

49/60

Registers description

TDA7529

6.1.21

AF state machine wait time 1 (20 / 36)

Table 46. AF state machine wait time 1 (20 / 36)

MSB

D₇

LSB

Function

D₆

D₅

D₄

D₃

D₂

D₁

D₀

X

Not used

X

WAIT 1ms

0

1

0

1

0

0.04ms (min. value)

1ms (default value)

6.1.22

PLL main divider (N-divider) 1 (21 / 37)

Table 47. PLL main divider (N-divider) 1 (21 / 37)

MSB

D₇

LSB

D₀

Function

D₆

D₅

D₄

D₃

D₂

D₁

Divider N value

X

M8

X

M9

X

M10

M11

M12

M13

M14

M15

X

6.1.23

PLL main divider (N-divider) 2 (22 / 38)

Table 48. PLL main divider (N-divider) 2 (22 / 38)

MSB

D₇

LSB

D₀

Function

D₆

D₅

D₄

D₃

D₂

D₁

Divider N value

X

M0

M1

M2

M3

M4

M5

M6

M7

X

50/60

TDA7529

Registers description

6.1.24

PLL main divider (N-divider) 3 (23 / 39)

Table 49. PLL main divider (N-divider) 3 (23 / 39)

MSB

D₇

LSB

D₀

Function

D₆

D₅

D₄

D₃

D₂

D₁

Divider N value

X

A0

A1

A2

A3

A4

X

6.1.25

PLL Divider ratio calculation

Table 50. PLL Divider ratio calculation

M counter

A counter

Notes

N= 32*P + A M=32

M16 M15

…

M7

…

M1

M0

A4

A3

A2

A1

A0 N= M*P + A M>32

(P=32)

6.1.26

VCO divider (V-divider) (24 / 40)

Table 51. VCO divider (V-divider) (24 / 40)

MSB

LSB

D₀

Function

D₇

D₆

D₅

D₄

D₃

D₂

D₁

Divider V value

X

V0

V1

V2

V3

V4

V5

V6

X

VCO range selection

Range 2

0

1

Range 1

51/60

Registers description

TDA7529

6.1.27

Charge pump current (25 / 41)

Table 52. Charge pump current (25 / 41)

MSB

LSB

D₀

Function

D₇

D₆

D₅

D₄

D₃

D₂

D₁

Low current charge pump

X

50 µA

X

100 µA

200 µA

400 µA

X

High current charge pump

X

0.5 mA

1mA

X

2mA

X

4mA

6.1.28

Tuning DAC 1 (26 / 42)

Table 53. Tuning DAC 1 (26 / 42)

MSB

LSB

D₀

Function

D₇

D₆

D₅

D₄

D₃

D₂

D₁

DAC 1 voltage 8..1

DAC1_.

X

DAC1_2

X

DAC1_3

X

DAC1_4

X

DAC1_5

X

DAC1_6

X

DAC1_7

X

DAC1_8

52/60

TDA7529

Registers description

6.1.29

Tuning DAC 2 (27 / 43)

Table 54. Tuning DAC 2 (27 / 43)

MSB

LSB

D₀

Function

D₇

D₆

D₅

D₄

D₃

D₂

D₁

DAC 2 voltage 8..1

DAC2_1

X

DAC2_2

X

DAC2_3

X

DAC2_4

X

DAC2_5

X

DAC2_6

X

DAC2_7

X

DAC2_8

6.1.30

6.1.31

DAC output voltage = 600mV + DACval * 9mV

Different controls (28 / 44)

Table 55. Different controls (28 / 44)

MSB

LSB

D₀

Function

D₇

D₆

D₅

D₄

D₃

D₂

D₁

DAC 1 On / Off

0

1

Off

On

DAC 2 On / Off

0

1

Off

On

X

DAC 1_0

DAC 2_0

Not used

X

IQ phase select

I anticipates Q

Q anticipates I

0

1

53/60

Registers description

TDA7529

6.1.32

Misc 3 (29 / 45)

Table 56. Misc 3 (29 / 45)

MSB

LSB

D₀

Function

D₇

D₆

D₅

D₄

D₃

D₂

D₁

PLL N divider MSB

X

M16

X

Not used

WAIT 2ms

0

1

0

1

0

1

0

1

0

1

0

1

0.08ms (min. value)

2ms (default value)

5.04ms (default value)

6.1.33

Analog test select (30 / 46)

Table 57. Analog test select (30 / 46)

MSB

LSB

D₀

Function

D₇

D₆

D₅

D₄

D₃

D₂

D₁

Analog test output signal select

0

1

0

1

0

1

IF AGC

FM AGC

AMAGC

DAC voltage of ADC

WAIT 0.5ms

0

1

0

1

0

1

0

1

0

1

0

1

0.02ms (min. value)

0.5ms (default value)

5.06ms (max value)

54/60

TDA7529

Registers description

6.1.34

AD converter test (31 / 47)

Table 58. AD converter test (31 / 47)

MSB

LSB

D₀

Function

D₇

D₆

D₅

D₄

D₃

D₂

D₁

ADC DAC direct programming

X

DAC 0

DAC 1

DAC 2

DAC 3

DAC 4

DAC 5

X

ADC test enable

0

1

Off

On

AGC test enable

0

1

Off

On

6.1.35

Read 1 (48)

Table 59. Read 1 (48)

MSB

LSB

D₀

Function

D₇

D₆

D₅

D₄

D₃

D₂

D₁

Mask set revision

0

1

0

1

0

1

A

B

C

D

Metal mask revision

0

1

0

1

0

1

A

B

C

D

GPIO 5 level

0

1

low

high

GPIO 6 level

low

0

1

high

55/60

Registers description

TDA7529

6.1.36

Read 2 (49)

Table 60. Read 2 (49)

MSB

LSB

D₀

Function

D₇

D₆

D₅

D₄

D₃

D₂

D₁

AD converter result

ADC0

X

ADC1

X

ADC2

X

ADC3

X

ADC4

X

ADC5

AD converter result status

0

1

Not OK

OK

56/60

TDA7529

Application schematic

7

Application schematic

Figure 17. Application schematic

B U S

T C I F 2

4 9

G n d R O

3 2

I F d e c

5 0

G P 1

3 1

I F i n 4

5 1

V C C P L L

3 0

V C C I F

5 2

G n d P L L

2 9

I F i n 3

5 3

L F H C

2 8

B I A S D 1

L F L C

2 7

1 0 0 n F C 5

5 4

I F i n 2

5 5

V C O g n d

2 6

V C O d e c 2

2 5

V t u n e

2 4

V C O d e c 1

2 3

V C C R F 1

2 2

A F S A M P L E

2 1

A F H O L D

2 0

A M A G C 2 / G P 8

1 9

2 2 u F

C 7 6

G P 2 / K e y

I F i n 1

G P 5

5 6

G P 2 / K e y

5 7

5 8

5 9

6 0

6 1

6 2

6 3

6 4

G P 5

G N D R F 2

T C A M

T C F M

V C C R F 2

B A L U N o u t 1

B A L U N o u t 2

C 8

1 u F

C 7

M P L E A F S A

A F H O L D

G P 4 / V D S

1 8

I F A G C 2

1 7

RF

a

B L M M 1 8 B D 1 0 2 S N 1 m u R a t

3

1

3

2

1

K P 2 3 1 1 E T o k o

D 2

T o k o

D 1

K P 2 3 1 1 E

1

2

F M A N T

1 8 0 n H T o k o L L Q 2 0 1 2 - F R 1 8

57/60

Package information

TDA7529

8

Package information

®

In order to meet environmental requirements, ST offers these devices in ECOPACK

packages. These packages have a Lead-free second level interconnect. The category of

second Level Interconnect is marked on the package and on the inner box label, in

compliance with JEDEC Standard JESD97. The maximum ratings related to soldering

conditions are also marked on the inner box label. ECOPACK is an ST trademark.

ECOPACK specifications are available at: www.st.com.

Figure 18. LQFP64 (10x10x1.4mm) exposed pad down mechanical data and package

dimensions (exposed pad size for D2 and E2: 4.5mm max.)

mm

inch

DIM.

OUTLINE AND

MECHANICAL DATA

MIN.

TYP. MAX. MIN.

0.150 0.0020

TYP. MAX.

0.0059

A1

A2

b

0.050

1.350 1.400 1.450 0.0531 0.0551 0.0571

0.170 0.220 0.270 0.0067 0.0087 0.0106

c

0.090

0.200 0.0035

0.0079

D

11.800 12.000 12.200 0.4646 0.4724 0.4803

9.800 10.000 10.200 0.3858 0.3937 0.4016

According to Pad size

D1

D2

D3

E

7.500

0.2953

11.800 12.000 12.200 0.4646 0.4724 0.4803

9.800 10.000 10.200 0.3858 0.3937 0.4016

According to Pad size

E1

E2

E3

e

7.500

0.500

0.2953

0.0197

L

0.450 0.600 0.750 0.0177 0.0236 0.0295

L1

k

1.000

0.0394

3.500 7.000

0.080

0.1378 0.2756

0.0031

LQFP64 (10x10x1.4mm)

Exposed Pad Down

ccc

Note: 1. Exact shape of each corner is optional.

7278841 C

58/60

TDA7529

Revision history

9

Revision history

Table 61. Document revision history

Date

Revision

Changes

7-Mar-2007

1

Initial release.

59/60

TDA7529

Please Read Carefully:

Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the

right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any

time, without notice.

All ST products are sold pursuant to ST’s terms and conditions of sale.

Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no

liability whatsoever relating to the choice, selection or use of the ST products and services described herein.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this

document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products

or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such

third party products or services or any intellectual property contained therein.

UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED

WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED

WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS

OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT

RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING

APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,

DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE

GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.

Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void

any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any

liability of ST.

ST and the ST logo are trademarks or registered trademarks of ST in various countries.

Information in this document supersedes and replaces all information previously supplied.

The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.

STMicroelectronics group of companies

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -

Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America

www.st.com

60/60

型号:	TDA7529
Brand Name：	STMicroelectronics
是否Rohs认证：	符合
生命周期：	Active
零件包装代码：	QFP
包装说明：	10 X 10 MM, 1.40 MM HEIGHT, LEAD FREE, LQFP-64
针数：	64
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	5.04
模拟集成电路 - 其他类型：	ANALOG CIRCUIT
JESD-30 代码：	S-PQFP-G64
长度：	10 mm
功能数量：	1
端子数量：	64
最高工作温度：	105 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	HLFQFP
封装形状：	SQUARE
封装形式：	FLATPACK, HEAT SINK/SLUG, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified
座面最大高度：	1.6 mm
最大供电电压 (Vsup)：	5.35 V
最小供电电压 (Vsup)：	4.7 V
标称供电电压 (Vsup)：	5 V
表面贴装：	YES
技术：	BICMOS
温度等级：	INDUSTRIAL
端子形式：	GULL WING
端子节距：	0.5 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	10 mm
Base Number Matches：	1

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