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    产品型号W83176R-251的Datasheet PDF文件预览

    W83176R-251  
    DDR/SDRAM BUFFER FOR VIA PRO266 CHIPSET  
    1.0 GENERAL DESCRIPTION  
    The W83176R-251 is a 2.5V/3.3V Clock buffer designed for VIA Pro266 chipset. W83176R-251 can  
    support 4 D.D.R. DRAM DIMMs or 2 standard SDRAM and 2 D.D.R. DRAM DIMMs.  
    W83176R-251 can be incorporated with W83194BR-250 which is the step-less clock with free  
    programmable CPU/AGP/PCI freq. outputs.  
    The W83176R-251 provides I2C serial bus interface to program the registers to enable or disable each  
    clock outputs. The W83176R-251 accepts a reference clock as its input and runs on a 3.3V or 2.5V  
    supply.  
    2.0 PRODUCT FEATURES  
    ·
    ·
    ·
    ·
    ·
    ·
    One input to 24 output buffer  
    Supports up to 4 D.D.R. DIMMs or 2 SDRAM DIMMs and 2 D.D.R. DIMMs  
    One additional output for feedback  
    Low Skew outputs (< 100ps)  
    Supports 266MHz D.D.R. SDRAM  
    I2C 2-Wire serial interface and I2C read back  
    ·
    ·
    Power management pin for power down control  
    48-pin SSOP package  
    Publication Release Date: Nov. 2000  
    Revision 0.32  
    - 1 -  
    W83176R-251  
    PRELIMINARY  
    3.0 PIN CONFIGURATION  
    FB_output  
    Vdd3.3_2.5  
    SEL_DDR  
    VDD2.5  
    Vss  
    1
    2
    3
    4
    5
    6
    7
    8
    9
    48  
    47  
    46  
    Vss  
    DDR0T  
    DDR0C  
    45  
    DDR11T  
    DDR11C  
    DDR10T  
    DDR10C  
    Vdd2.5  
    Vss  
    DDR9T  
    DDR9C  
    Vdd2.5  
    PD#  
    44  
    43  
    42  
    41  
    40  
    39  
    38  
    DDR1T_SRAM0  
    DDR1C_SRAM1  
    Vdd3.3_2.5  
    Vss  
    DDR2T_SRAM2  
    10  
    11  
    12  
    DDR2C_SRAM3  
    37  
    Vdd3.3_2.5  
    Buffer_IN  
    Vss  
    13  
    14  
    15  
    16  
    17  
    18  
    19  
    20  
    21  
    22  
    23  
    24  
    36  
    35  
    34  
    33  
    32  
    31  
    30  
    29  
    28  
    27  
    26  
    25  
    Vss  
    DDR8T  
    DDR8C  
    Vdd2.5  
    Vss  
    DDR7T  
    DDR7C  
    DDR6T  
    DDR6C  
    Vss  
    DDR3T_SRAM4  
    DDR3C_SRAM5  
    Vdd3.3_2.5  
    Vss  
    DDR4T_SRAM6  
    DDR4C_SRAM7  
    DDR5T  
    DDR5C  
    Vdd3.3_2.5  
    SCLK  
    SDATA  
    *: internal pull-up  
    4.0 PIN DESCRIPTION  
    IN - Input  
    OUT - Output  
    I/O - Bi-directional Pin  
    # - Active Low  
    W
    *- Internal 250k pull-up  
    Publication Release Date: Nov. 2000  
    Revision 0.32  
    - 2 -  
    W83176R-251  
    PRELIMINARY  
    4.1 Pin Description  
    SYMBOL  
    PIN  
    I/O  
    FUNCTION  
    SEL_DDR  
    48  
    IN  
    1= DDR only mode  
    0=Standard SDRAM mode  
    When SEL_DDR is pulled high. Pin 4,5,6,7,10,11,15,  
    16,19,20,21,22,27,28,29,30,33,34,38,39,42,43,44  
    and 45 will be D.D.R. outputs. Vdd3.3_2.5 should be  
    connected to 2.5V for DDR power supply.  
    When SEL_DDR is pulled low. Pin  
    6,7,10,11,15,16,19 and 20 will be standard SDRAM  
    outputs. Pin27,28,29,30,33,34,39,42,43,44 and 45  
    will be DDR outputs, Pin 4,5,21,22 will be Three-  
    Stated.  
    Vdd3.3_2.5 should be connected to 3.3V for SDRAM.  
    SDATA  
    SCLK  
    24  
    25  
    13  
    I/O  
    IN  
    Serial data of I2C 2-wire control interface  
    Serial clock of I2C 2-wire control interface  
    Buffer_IN  
    IN  
    Reference input from chipset. 2.5V input for DDR  
    only mode. 3.3V for standard SDRAM mode.  
    FB_output  
    PD#  
    1
    OUT Feedback clock for chipset. Output voltage depends  
    on Vdd3.3_2.5  
    36  
    IN  
    Active LOW input to enable Power Down mode; all  
    outputs will be Three-Stated  
    DDR[0,5:11]T  
    DDR[0,5:11]C  
    4,21,28,30,34, OUT Clock outputs. Copies of Buffer_IN.  
    39,43,45  
    5,22,27,29,33, OUT Complementary copies of Buffer_IN  
    38,42,44  
    DDR[1:4]T_SDRAM  
    [0,2,4,6]  
    6,10,15,19  
    OUT Clock outputs. Copies of Buffer_IN. Voltage dpends  
    on the Vdd3.3_2.5  
    DDR[1:4]C_SDRAM  
    [0,2,4,6]  
    7,11,16,20  
    OUT Clock outputs.  
    SEL_DDR=1, these pins are complementary copies  
    of Buffer_IN.  
    SEL_DDR=0, these pins are copies of Buffer_IN.  
    Voltage dpends on the Vdd3.3_2.5  
    4.5 Power Pins  
    SYMBOL  
    PIN  
    FUNCTION  
    Vdd3.3_2.5  
    2,8,12,17,23  
    Connected to 2.5V when SEL_DDR=1 and 3.3V when  
    SEL_DDR=0  
    Vdd2.5  
    32,37,41,47  
    Power supply 2.5V.  
    Publication Release Date: Nov. 2000  
    - 3 -  
    Revision 0.32  
    W83176R-251  
    PRELIMINARY  
    Vss  
    3,9,14,18,26,31,35, Ground  
    40,46  
    Publication Release Date: Nov. 2000  
    Revision 0.32  
    - 4 -  
    W83176R-251  
    PRELIMINARY  
    5.1 Register 4 : Control Register (default = 1)  
    Bit  
    @PowerUp  
    Pin  
    Description  
    SEL_DDR (Active / Inactive)  
    7
    1
    0
    0
    0
    1
    1
    1
    1
    48  
    -
    6
    5
    4
    3
    2
    1
    0
    Reserved  
    -
    Reserved  
    -
    Reserved  
    45,44  
    43,42  
    39,38  
    34,33  
    DDR11T,DDR11C(Active / Inactive)  
    DDR10T,DDR10C(Active / Inactive)  
    DDR9T,DDR9C(Active / Inactive)  
    DDR8T,DDR8C(Active / Inactive)  
    5.2 Register 5: Control Register ( 1 = enable, 0 = Stopped )  
    Bit  
    7
    @PowerUp  
    Pin  
    Description  
    DDR7T,DDR7C(Active / Inactive)  
    1
    1
    1
    1
    30,39  
    28,27  
    21,22  
    19,20  
    6
    DDR6T,DDR6C(Active / Inactive)  
    DDR5T,DDR5C(Active / Inactive)  
    5
    4
    DDR4T_SDRAM6,  
    DDR4C_SDRAM7 (Active / Inactive)  
    DDR3T_SDRAM4,  
    3
    2
    1
    0
    1
    1
    1
    1
    15,16  
    10,11  
    6,7  
    DDR3C_SDRAM5 (Active / Inactive)  
    DDR2T_SDRAM2,  
    DDR2C_SDRAM3 (Active / Inactive)  
    DDR1T_SDRAM0,  
    DDR1C_SDRAM1 (Active / Inactive)  
    DDR0T,DDR0C(Active / Inactive)  
    4,5  
    Publication Release Date: Nov. 2000  
    Revision 0.32  
    - 5 -  
    W83176R-251  
    PRELIMINARY  
    6.0 ORDERING INFORMATION  
    Part Number  
    Package Type  
    Production Flow  
    W83176R-251  
    48 PIN SSOP  
    °
    °
    Commercial, 0 C to +70 C  
    7.0 HOW TO READ THE TOP MARKING  
    W83176R-251  
    28051234  
    814GAB  
    1st line: Winbond logo and the type number: W83176R-251  
    2nd line: Tracking code 2 8051234  
    2
    : wafers manufactured in Winbond FAB 2  
    8051234  
    : wafer production series lot number  
    3rd line: Tracking code 814 G B B  
    814  
    : packages made in '98, week 14  
    G
    : assembly house ID; O means OSE, G means GR  
    A
    : Internal use code  
    B
    : IC revision  
    All the trade marks of products and companies mentioned in this data sheet belong to their  
    respective owners  
    .
    Publication Release Date: Nov. 2000  
    Revision 0.32  
    - 6 -  
    W83176R-251  
    PRELIMINARY  
    8.0 PACKAGE DRAWING AND DIMENSIONS  
    Headquarters  
    No. 4, Creation Rd. III  
    Science-Based Industrial Park  
    Hsinchu, Taiwan  
    TEL: 886-35-770066  
    FAX: 886-35-789467  
    www: http://www.winbond.com.tw/  
    Winbond Electronics  
    (North America) Corp.  
    2730 Orchard Parkway  
    San Jose, CA 95134 U.S.A.  
    TEL: 1-408-9436666  
    Winbond Electronics (H.K.) Ltd.  
    Rm. 803, World Trade Square, Tower II  
    123 Hoi Bun Rd., Kwun Tong  
    Kowloon, Hong Kong  
    TEL: 852-27516023-7  
    FAX: 852-27552064  
    FAX: 1-408-9436668  
    Taipei Office  
    11F, No. 115, Sec. 3, Min-Sheng East Rd.  
    Taipei, Taiwan  
    TEL: 886-2-7190505  
    FAX: 886-2-7197502  
    TLX: 16485 WINTPE  
    Please note that all data and specifications are subject to change without notice. All the trade  
    marks of products and companies mentioned in this data sheet belong to their respective  
    owners  
    .
    These products are not designed for use in life support appliances, devices, or systems  
    where malfunction of these products can reasonably be expected to result in personal injury.  
    Winbond customers using or selling these products for use in such applications do so at their  
    own risk and agree to fully indemnify Winbond for any damages resulting from such improper  
    use or sale.  
    Publication Release Date: Nov. 2000  
    - 7 -  
    Revision 0.32  
    配单直通车
    W83176R-251产品参数
    型号:W83176R-251
    生命周期：Obsolete
    零件包装代码：SSOP
    包装说明：SSOP,
    针数：48
    Reach Compliance Code：unknown
    HTS代码：8542.39.00.01
    风险等级：5.84
    输入调节：STANDARD
    JESD-30 代码：R-PDSO-G48
    JESD-609代码：e3
    长度：15.875 mm
    逻辑集成电路类型：LOW SKEW CLOCK DRIVER
    功能数量：1
    反相输出次数：12
    端子数量：48
    实输出次数：12
    最高工作温度：70 °C
    最低工作温度：
    封装主体材料：PLASTIC/EPOXY
    封装代码：SSOP
    封装形状：RECTANGULAR
    封装形式：SMALL OUTLINE, SHRINK PITCH
    认证状态：Not Qualified
    Same Edge Skew-Max（tskwd）：0.1 ns
    座面最大高度：2.794 mm
    标称供电电压 (Vsup)：2.5 V
    表面贴装：YES
    温度等级：COMMERCIAL
    端子面层：MATTE TIN
    端子形式：GULL WING
    端子节距：0.635 mm
    端子位置：DUAL
    宽度：7.5 mm
    Base Number Matches：1
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