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W83194BR-K8/W83194BG-K8

Winbond Clock Generator for AMD^®

K8™ Microprocessors and Chipsets

Date: 05/02/2006 Revision: 0.61

W83194BR-K8/W83194BG-K8

CLOCK GEN. FOR AMD^®K8™ MICROPROCESSORS AND CHIPSET

W83194BR-K8 Datasheet Revision History

PAGES

n.a.

DATES

VERSION

WEB

VERSION

MAIN CONTENTS

1

06/08/2004 0.5

n.a.

All of the versions before 0.50 are for

internal use.

2

1-16,19

03/31/2005 0.6

05/02/2006 0.61

n.a.

Please see red text.

3

Add Lead free part

4

5

6

7

8

9

10

Publication Release Date: May 2006

Revision 0.61

- I -

W83194BR-K8/W83194BG-K8

CLOCK GEN. FOR AMD^®K8™ MICROPROCESSORS AND CHIPSET

Table of Contents-

1. GENERAL DESCRIPTION................................................................................................................. 1

2. PRODUCT FEATURES ..................................................................................................................... 1

3. PIN CONFIGURATION ...................................................................................................................... 2

4. BLOCK DIAGRAM ............................................................................................................................. 3

5. PIN DESCRIPTION............................................................................................................................ 4

5.1 Crystal I/O...........................................................................................................................................4

5.2 CPU, PCI/HT66, PCI Clock Outputs .................................................................................................4

5.3 Fixed Frequency Outputs and Function Control pin.........................................................................5

5.4 I²C Control Interface...........................................................................................................................6

5.5 Power and GND Pins.........................................................................................................................6

5.6 HTTSEL table.....................................................................................................................................6

6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE ....................................................... 7

7. I²C CONTROL AND STATUS REGISTERS...................................................................................... 9

7.1 Register 0: Frequency Select (Default = 38h)...................................................................................9

7.2 Register 1: CPU & PCI_F Control (1 = Enable, 0 = Disable) & FS0~FS3 latch (Default = E7h) ....9

7.3 Register 2: PCI Control (1 = Enable, 0 = Disable) (Default = FFh) ................................................10

7.4 Register 3: HTTCLK, REF (1 = Enable, 0 = Disable) (Default = FFh) ...........................................10

7.5 Register 4: 24_48MHz Control (1 = Enable, 0 = Disable) (Default = F8h).....................................10

7.6 Register 5: Watchdog Control (Default = 00h)................................................................................11

7.7 Register 6: Watchdog Timer (Default = 08h) ..................................................................................11

7.8 Register 7: M/N Program (Default = 8Bh).......................................................................................12

7.9 Register 8: M/N Program (Default = 30h)........................................................................................12

7.10 Register 9: Spread Spectrum Programming (Default = 1Fh) .........................................................12

7.11 Register 10: Divisor and Step-less Enable Control (Default = 01h) ...............................................13

7.12 Register 11: Spread Spectrum Programming (Default = CAh) ......................................................14

7.13 Register 12: SKEW Control (Default = 84h)....................................................................................14

7.14 Register 13: Winbond Chip ID (Default = 46h) (Read Only)...........................................................15

7.15 Register 14: Winbond Chip ID (Default = 55h) (Read Only)...........................................................15

7.16 Register 15: REF & PCI Output Slew-Rate control (Default = 25h)...............................................16

7.17 Register 16: HTTCLK & 24_48MHz Slew-Rate control (Default = 95h) ........................................16

7.18 Register 17: Slew Rate Control (Default = AAh).............................................................................16

8. ACCESS INTERFACE ..................................................................................................................... 17

8.1 Block Write protocol .........................................................................................................................17

8.2 Block Read protocol.........................................................................................................................17

- II -

W83194BR-K8/W83194BG-K8

CLOCK GEN. FOR AMD^®K8™ MICROPROCESSORS AND CHIPSET

8.3 Byte Write protocol...........................................................................................................................17

8.4 Byte Read protocol...........................................................................................................................17

9. SPECIFICATIONS ........................................................................................................................... 18

9.1 ABSOLUTE MAXIMUM RATINGS .................................................................................................18

9.2 DC Operating Characteristics..........................................................................................................18

9.3 Clock Skews.....................................................................................................................................19

9.4 CPU Clock Electrical Characteristics...............................................................................................20

9.5 HTTCLK Clock Electrical Characteristics........................................................................................21

9.6 PCI Clock Electrical Characteristics ................................................................................................21

9.7 24M, 48M Clock Electrical Characteristics......................................................................................22

9.8 REF Electrical Characteristics .........................................................................................................22

10.ORDERING INFORMATION............................................................................................................ 23

11.HOW TO READ THE TOP MARKING............................................................................................. 23

12.PACKAGE DRAWING AND DIMENSIONS..................................................................................... 24

Publication Release Date: May 2006

- III -

Revision 0.61

W83194BR-K8/W83194BG-K8

CLOCK GEN. FOR AMD^®K8™ MICROPROCESSORS AND CHIPSET

1. GENERAL DESCRIPTION

The W83194BR-K8 is a Clock Synthesizer for AMD ATHLON 64™ and OPTERON™ Processors and

support chipsets. W83194BR-K8 provides all clocks required for the high-speed microprocessors

and provides step-less frequency programming and 32 different frequencies of CPU, HTTCLK and

PCI clock settings. All clocks are externally selectable with smooth transitions.

The W83194BR-K8 provides I²C serial bus interface to program the registers to enable or disable

each clock outputs and provides 1% & 0.5% center type and down type spread spectrum or

programmable S.S.T. scale to reduce EMI.

The W83194BR-K8 also has watchdog timer and reset output pin to support auto-reset when systems

stop functioning caused by improper frequency setting.

The W83194BR-K8 accepts a 14.318 MHz reference crystal as its input and runs on 3.3V supply.

2. PRODUCT FEATURES

• 2 pairs push-pull differential clock for CPU and Chipset

• 3 selectable PCI/HTTCLK clock outputs

• 1 HTTCLK clock output

• 9 PCI synchronous clocks, 1 free running

• 1 48MHz clock outputs

• 1 24_48MHz for I/O chip, default 24MHz

• 3 REF 14.318MHz clock outputs

• I²C 2-wire serial interface supports block and byte mode read/write

• Step-less frequency programming

• Smooth frequency switch with selections from 100 to 309MHz

• Programmable clock outputs slew rate control and skew control

• Support 1% & 0.5% center type and down type spread spectrum in table mode

• Programmable S.S.T. scale to reduce EMI in M/N mode

• Programmable registers to enable/disable each output and select modes

• Watch dog timer and RESET# output pins

• 48-pin SSOP package

Publication Release Date: May 2006

- 1 -

Revision 0.61

W83194BR-K8/W83194BG-K8

CLOCK GEN. FOR AMD^®K8™ MICROPROCESSORS AND CHIPSET

3. PIN CONFIGURATION

*FS0/REF0

V D D REF

1

2

3

4

5

6

7

8

9

48 REF1/*FS1

47 G N D

46 V D D REF

45 REF2/*FS2

44 RESET#

43 V D D A

X IN

X O U T

G N D

*H TTSEL_0/H TTCLK_0

*H TTSEL_1/PCI_7/H TTCLK_1

PCI_8/H TTCLK_2

V D D PCI

42 G N D A

41 CPU CLK_T0

40 CPU CLK_C0

39 G N D

38 V D D CPU

37 CPU CLK_T1

36 CPU CLK_C1

35 V D D CPU

34 G N D

G N D 10

PCI_9/H TTCLK_3 11

PCI_10 12

PCI_0 13

PCI_1 14

G N D 15

V D D PCI 16

PCI_2 17

PCI_3 18

V D D PCI 19

G N D 20

33 G N D

32 PD #

31 48M H z/^&FS3

30 G N D

29 V D D 48

PCI_4 21

PCI_5 22

28 24_48M H z/*SEL24_48#

27 G N D

*PCISEL#/PCI_F 23

*PCI_STO P#/PCI_6 24

26 *SD A TA

25 *SCLK

#: Active low

*: Internal pull up resistor 120KΩ to VDD

^&: Internal Pull-down resistor 120KΩ to GND

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W83194BR-K8/W83194BG-K8

CLOCK GEN. FOR AMD^®K8™ MICROPROCESSORS AND CHIPSET

4. BLOCK DIAGRAM

D

iv id e r

2

3

4 8 M

2 4 _ 4 8 M

H

z ,

H

P L L 2

X T A L

z

X I N

R

E F 0 : 2

O

S C

X O

U

T

P L L 1

S p r e a d

S p e c t r u m

V

C O C L K

2

C

P U

C

L K _ T 0 : 1

L K _ C 0 : 1

3

P C I _ 7 : 9 / H T T C L K _ 1 : 3

M

/ N

R

R a t io

O

M

D

iv id e r

H

T T C L K _ 0

* P C I S E L #

* H T T S E L _ 0 : 1

F S [0 : 3 ]

L a t c h

P O

8

&

R

P C I _ 0 : 6 ,

P C I _ 1 0

* S E L 2 4 _ 4 8 #

P C I_ F

C

o n t r o l

* P D

* P C I _ S T O

#

L o g ic

P

& C o n f ig

e g is t e r

R

E S E T #

R

* S D A T A

* S C L K

I 2 C

I n t e r f a c e

Publication Release Date: May 2006

Revision 0.61

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W83194BR-K8/W83194BG-K8

CLOCK GEN. FOR AMD^®K8™ MICROPROCESSORS AND CHIPSET

5. PIN DESCRIPTION

BUFFER TYPE SYMBOL

DESCRIPTION

IN

IN_td120k

IN_tp120k

OUT

I/O

Input

Latch input pin and internal 120KΩ pull down

Latch input pin and internal 120KΩ pull up

Output

Bi-directional Pin

I/OD

OD

Bi-directional Pin, Open Drain

Open Drain

#

Active Low

*

&

Internal 120kΩ pull-up

Internal 120kΩ pull-down

5.1 Crystal I/O

PIN NAME

TYPE

DESCRIPTION

3

XIN

IN Crystal input with internal loading capacitors and feedback

resistors.

4

XOUT

OUT Crystal output at 14.318MHz nominally with internal loading

capacitors.

5.2 CPU, PCI/HT66, PCI Clock Outputs

PIN NAME

CPUCLK_T 0:1

CPUCLK_C 0:1

HTTCLK_0

TYPE

DESCRIPTION

41,37,40,3

6

OUT

3.3V push-pull differential clock outputs for CPU and

Chipset.

6

7

OUT

3.3V HTTCLK output clock

*HTTSEL_0

IN_tp120kLatched input at initial power up for PCI/HTTCLK

selecting the output frequency clocks. This pin has

internal 120KΩ pull up.

PCI_7/HTTCLK_1

*HTTSEL_1

OUT

3.3V PCI 33MHz or HTTCLK (default) output clock

select by HTTSEL [0:1]

IN_tp120kLatched input at initial power up for PCI/HTTCLK

selecting the output frequency clocks. This pin has

internal 120KΩ pull up.

8,11

PCI_8:9/HTTCLK

_2:3

OUT

3.3V PCI 33MHz(default) or HTTCLK output clocks

select by HTTSEL [0:1]

13, 14, 17,

18, 21,

PCI_0:5

PCI_10

OUT

3.3V PCI clock outputs,

22,12

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W83194BR-K8/W83194BG-K8

CLOCK GEN. FOR AMD^®K8™ MICROPROCESSORS AND CHIPSET

CPU, PCI/HT66, PCI Clock Outputs, continued.

PIN NAME

PCI_F

TYPE

DESCRIPTION

23

OUT 3.3V Free-Run PCI clock output, not affected by PCI_STOP#.

*PCISEL#

IN_tp120kLatched input at initial power up for pin 24 PCI_STOP/PCI_6

selecting the output, This pin has internal 120KΩ pull up, when

PCISEL# = 0 pin24 is PCI_6, = 1 pin 24 is PCI_STOP#(default)

24

PCI_6

OUT 3.3V PCI clock outputs,

*PCI_STOP# IN_tp120kInput pins; when low, stop all PCI clock except PCI_F (pin 23);

This pin has internal 120KΩ pull up (default).

5.3 Fixed Frequency Outputs and Function Control pin

PIN NAME

REF0

TYPE

DESCRIPTION

1

OUT 14.318MHz output.

*FS0

IN_tp120kLatched input for FS0 at initial power up selecting the output

frequency clocks. This pin has internal 120KΩ pull up.

48

REF1

*FS1

OUT 14.318MHz output.

IN_tp120kLatched input for FS1 at initial power up selecting the output

frequency clocks. This pin has internal 120KΩ pull up.

45

28

REF2

*FS2

OUT 14.318MHz clock output.

IN_tp120kLatched input for FS2 at initial power up selecting the output

frequency clocks. This pin has internal 120KΩ pull up.

24_48MHz

OUT 24 or 48MHz clock output,

*SEL24_48#

IN_tp120kLatched input for 24_48MHz at initial power up selecting the

output frequency clocks. This pin has internal 120KΩ pull up, 1

= 24 MHz (default), 0= 48MHz.

31

32

48MHz

^&FS3

OUT 48MHz clock output.

IN_td120kLatched input for FS3 at initial power up selecting the output

frequency clocks. This pin has internal 120KΩ pull down.

*PD#

IN_tp120kLow active input pin used to power down the device into a low

power state. The internal clocks are disabled and the VCO and

the crystal oscillator are stopped. This pin has internal 120KΩ

pull up.

44

RESET#

OD

250mS low level system reset signal when Watchdog Timer

times out. Application circuit must add external pull high.

Publication Release Date: May 2006

- 5 -

Revision 0.61

W83194BR-K8/W83194BG-K8

CLOCK GEN. FOR AMD^®K8™ MICROPROCESSORS AND CHIPSET

5.4 I²C Control Interface

PIN NAME

TYPE

DESCRIPTION

26

*SDATA

I/OD Serial data of I²C 2-wire control interface with internal pull-up

resistor

25

*SCLK

IN Serial clock of I²C 2-wire control interface with internal pull-up

resistor

5.5 Power and GND Pins

PIN NAME

VDDREF

VDDPCI

VDD48

VDDCPU

VDDA

DESCRIPTION

3.3V power supply for REF.

2,46

9,16,19

3.3V power supply for PCI.

3.3V power supply for 48MHz.

3.3V power supply for CPU.

3.3V power supply analog core.

Ground pin for analog core.

Ground pin for 3.3V.

29

35,38

43

42

GNDA

5,10,15,20,27,30,33,34,39,47

GND

5.6 HTTSEL table

HTTSEL HTTSEL

PCI_7/HTTLK_1(PIN7)

PCI_8/HTTCLK_2(PIN8) PC_9I/HTTCLK_3(PIN11)

_0

_1

0

HTTCLK_1

PCI_7

HTTCLK_2

PCI_8

PCI_9

HTTCLK_3

PCI_9

0

1

0

1

HTTCLK_1

PCI_8

PCI_9

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W83194BR-K8/W83194BG-K8

CLOCK GEN. FOR AMD^®K8™ MICROPROCESSORS AND CHIPSET

6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE

This frequency table uses the power-on latched FS [3:0] value or register bits SSEL [4:0] (Register 0

bit 7 ~ 3). When FS [3:0] pins are no-connecting in the application circuit, CPU, HTTCLK and PCI

clock frequency will have the values shown in grey color.

BIT 7

FS4

0

BIT 6 BIT 5 BIT 4 BIT 3

CPU (MHZ)

HTTCLK (MHZ)

PCI (MHZ)

FS3

0

1

0

1

FS2

0

1

0

1

0

1

0

FS1

0

1

0

1

0

1

0

1

0

1

0

1

0

FS0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

100.9

133.9

168.0

202.0

100.2

133.5

166.7

200.4

150.0

180.0

210.0

240.0

270.0

233.3

266.6

300.0

100.0

133.3

166.6

200.0

103.0

137.3

171.6

206.0

154.5

67.27

66.95

67.2

33.63

33.47

33.6

0

67.33

66.8

33.66

33.4

0

66.75

66.68

66.8

33.34

33.4

0

60.0

30.0

0

60.0

30.0

0

70.0

35.0

0

60.0

30.0

0

67.50

66.67

75.0

33.75

33.33

37.5

0

1

66.67

68.67

68.66

68.67

61.8

33.33

34.33

30.9

1

Publication Release Date: May 2006

Revision 0.61

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W83194BR-K8/W83194BG-K8

CLOCK GEN. FOR AMD^®K8™ MICROPROCESSORS AND CHIPSET

Frequency Selection BY hardware or Software, continued.

BIT 7

BIT 6 BIT 5 BIT 4 BIT 3

CPU (MHZ)

HTTCLK (MHZ)

PCI (MHZ)

FS4

1

FS3

1

FS2

0

FS1

0

FS0

1

185.4

216.3

247.2

278.1

240.3

274.6

309.0

61.8

72.1

30.9

36.0

1

0

1

0

1

0

1

61.8

30.9

1

0

69.53

68.67

77.25

34.76

34.33

38.62

1

0

1

0

1

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W83194BR-K8/W83194BG-K8

CLOCK GEN. FOR AMD^®K8™ MICROPROCESSORS AND CHIPSET

7. I²C CONTROL AND STATUS REGISTERS

PWD: Power on default bit value.

7.1 Register 0: Frequency Select (Default = 38h)

BIT

7

NAME

SSEL 4

SSEL 3

SSEL 2

SSEL 1

SSEL 0

EN_SSEL

PWD

DESCRIPTION

Software frequency table selection through I²C

0

1

6

5

4

3

2

Enable software table selection FS [4:0].

0 = Hardware table setting.

1 = Software table setting through Bit 7~3.

EN_SPSP

1

0

Enable spread spectrum mode at clock outputs

0 = Spread Spectrum mode disable

1 = Spread Spectrum mode enable

EN_SAFE_FREQ

After watchdog timeout

0 = Reload the hardware FS [3:0] latched pins setting.

1 = Reload the frequency table selection as defined in Reg-5 Bit 4~0.

7.2 Register 1: CPU & PCI_F Control (1 = Enable, 0 = Disable) & FS0~FS3 latch

(Default = E7h)

BIT

7

NAME

PCI_FEN

CPUCLKEN1

CPUCLKEN0

FS4

PWD

1

DESCRIPTION

Pin 23 PCI_F output control

6

1

Pin 37,36 CPUCLK_T1/C1 output control

Pin 41,40 CPUCLK_T0/C0 output control

Fix in low level. (Read only)

5

1

4

0

3

^&FS3

X

Power on latched value of FS3 pin 31. (Read only)

Power on latched value of FS2 pin 45. (Read only)

Power on latched value of FS1 pin 48. (Read only)

Power on latched value of FS0 pin 1. (Read only)

2

*FS2

X

1

*FS1

X

0

*FS0

X

Publication Release Date: May 2006

Revision 0.61

- 9 -

W83194BR-K8/W83194BG-K8

CLOCK GEN. FOR AMD^®K8™ MICROPROCESSORS AND CHIPSET

7.3 Register 2: PCI Control (1 = Enable, 0 = Disable) (Default = FFh)

BIT

7

NAME

PWD

DESCRIPTION

Pin 24 PCI_6 output control

PCI_6EN

PCI_10EN

PCI_5EN

PCI_4EN

PCI_3EN

PCI_2EN

PCI_1EN

PCI_0EN

1

6

Pin 12 PCI_10 output control

Pin 22 PCI_5 output control

Pin 21 PCI_4 output control

Pin 18 PCI_3 output control

Pin 17 PCI_2 output control

Pin 14 PCI_1 output control

Pin 13 PCI_0 output control

5

4

3

2

1

0

7.4 Register 3: HTTCLK, REF (1 = Enable, 0 = Disable) (Default = FFh)

BIT

7

NAME

-

PWD

DESCRIPTION

Reserved for Winbond internal use, don’t modify it

Pin 45 REF2 output control

1

6

REF2EN

5

REF1EN

Pin 48 REF1 output control

4

REF0EN

Pin 1 REF0 output control

3

HTTCLK_0EN

HTTCLK_3EN

HTTCLK_2EN

HTTCLK_1EN

Pin 6 HTTCLK_0 output control

2

Pin 11 PCI_9/HTTCLK_3 output control

Pin 8 PCI_8/HTTCLK_2 output control

Pin 7 PCI_7/HTTCLK_1 output control

1

0

7.5 Register 4: 24_48MHz Control (1 = Enable, 0 = Disable) (Default = F8h)

BIT

NAME

PWD

DESCRIPTION

7

SEL_24

X

Pin 28 SEL24 _48 MHz output selection, 1: 24 MHz (default), 0: 48

MHz, Default values depend on latched value of SEL24_48# pin

duration power on reset.

6

5

4

3

2

1

0

24_48MEN

48EN

1

X

0

Pin 28 24_48MHz output control

Pin 31 48MHz output control

HTTSEL_0*

HTTSEL_1*

PCISEL#*

-

Pin 6 Power on latched value of HTTSEL_0* pin.

Pin 7 Power on latched value of HTTSEL_1* pin.

Pin 23 Power on latched value of PCISEL#* pin.

Reserved for Winbond internal use, don’t modify it

-

- 10 -

W83194BR-K8/W83194BG-K8

CLOCK GEN. FOR AMD^®K8™ MICROPROCESSORS AND CHIPSET

7.6 Register 5: Watchdog Control (Default = 00h)

BIT

7

NAME

-

PWD

DESCRIPTION

Reserved for Winbond internal use, user must not modify it

1: Enable Watchdog Timer.

0

6

EN_WD

0: Disable Watchdog Timer.

During timer count down reading this bit returns 1.

If count to zero, reading this bit returns 0.

Read only. Timeout Flag.

5

WD_TIMEOUT

0

1: Watchdog has ever started and counts to zero.

0: Watchdog is restarted and counting.

4

3

2

1

0

SAF_FREQ 4

SAF_FREQ 3

SAF_FREQ 2

SAF_FREQ 1

SAF_FREQ 0

0

When Watchdog Timer times out and EN_SAFE_FREQ=1, these bits

will be reloaded to Reg-0 bit 7~3 to select the clock frequencies.

7.7 Register 6: Watchdog Timer (Default = 08h)

BIT

7

NAME

PWD

DESCRIPTION

WD_TIME [7]

WD_TIME [6]

WD_TIME [5]

WD_TIME [4]

WD_TIME [3]

WD_TIME [2]

WD_TIME [1]

WD_TIME [0]

0

1

0

6

5

Watchdog Timer timeout duration. The bit resolution is 250mS. The

default time is 8*250mS = 2.0 seconds. If Watchdog Timer is started,

this register will down count. Reading this register will return the

down count value.

4

3

2

1

0

Publication Release Date: May 2006

- 11 -

Revision 0.61

W83194BR-K8/W83194BG-K8

CLOCK GEN. FOR AMD^®K8™ MICROPROCESSORS AND CHIPSET

7.8 Register 7: M/N Program (Default = 8Bh)

BIT

7

NAME

N_DIV<8>

M<6>

PWD

X

DESCRIPTION

Programmable N divisor value. Bit 7~0 are defined in the Register 8.

Programmable M divisor value.

6

X

5

M>5>

X

4

M<4>

X

3

M<3>

X

2

M<2>

X

1

M<1>

X

0

M<0>

X

7.9 Register 8: M/N Program (Default = 30h)

BIT

7

NAME

PWD

X

DESCRIPTION

N_DIV [7]

N_DIV [6]

N_DIV [5]

N_DIV [4]

N_DIV [3]

N_DIV [2]

N_DIV [1]

N_DIV [0]

6

X

5

X

4

X

Programmable N divisor value bit 7 ~0. The bit 8 is defined in Register 7,

bit 9~11 is defined in register 10 bit 3~5.

3

X

2

X

1

X

0

X

Note: About N value bit 9 ~ 11 descriptions only for Winbond internal and BOIS program use; the release version please

reserved this description.

7.10 Register 9: Spread Spectrum Programming (Default = 1Fh)

BIT

7

NAME

PWD

DESCRIPTION

Spread Spectrum Up Counter bit 3.

SP_UP [3]

0

1

6

SP_UP [2]

Spread Spectrum Up Counter bit 2.

Spread Spectrum Up Counter bit 1.

Spread Spectrum Up Counter bit 0

Spread Spectrum Down Counter bit 3

Spread Spectrum Down Counter bit 2

Spread Spectrum Down Counter bit 1

Spread Spectrum Down Counter bit 0

5

SP_UP [1]

4

SP_UP [0]

3

SP_DOWN [3]

SP_DOWN [2]

SP_DOWN [1]

SP_DOWN [0]

2

1

0

- 12 -

W83194BR-K8/W83194BG-K8

CLOCK GEN. FOR AMD^®K8™ MICROPROCESSORS AND CHIPSET

7.11 Register 10: Divisor and Step-less Enable Control (Default = 01h)

BIT

NAME

PWD

DESCRIPTION

7

EN_MN_PROG

0

0: using frequency table

1: using M/N register to synthesize clock frequency

The equation is VCO freq. = 14.318MHz * (N+4)/ M. Once the

watchdog timer times out, this bit will be cleared. Then the

frequency will be decided by hardware strapping FS<3:0> or

frequency select bits SAF_FREQ [4:0] when EN_SAFE_FREQ

(Reg0 - bit 0) is set

6

5

4

3

2

1

0

Reserved

N_DIV<11>

N_DIV<10>

N_DIV<9>

KVAL<2>

KVAL<1>

KVAL<0>

0

Reserved.

Programmable N divisor bit 11,10,9. Set these bits prior to enable

M/N programming method.

X

Define the CPU/HTTCLK/PCI divider ratio

Refer to Table-1

Note: This Byte 3:5 only for Winbond internal and BOIS program use; the release version please reserved this byte.

Table-1 CPU, HTTCLK, PCI divider ratio selection Table

KVAL2~KVAL0

CPU

2

HTTCLK

PCI

10

12

14

16

12

16

20

12

000

001

010

011

100

101

110

111

5

6

2

7

2

8

4

6

4

8

4

10

6

3

Publication Release Date: May 2006

Revision 0.61

- 13 -

W83194BR-K8/W83194BG-K8

CLOCK GEN. FOR AMD^®K8™ MICROPROCESSORS AND CHIPSET

7.12 Register 11: Spread Spectrum Programming (Default = CAh)

BIT

7

NAME

SPSP1

SPSP0

PWD

DESCRIPTION

Spread Spectrum type select.

1

00 : Down

10 : Center

1%,

01 : Down 0.5%

11 : Center 0.5%

6

5

4

3

2

1

0

SPCNT [5]

SPCNT [4]

SPCNT [3]

SPCNT [2]

SPCNT [1]

SPCNT [0]

0

1

0

1

0

Spread Spectrum Programmable time, the resolution is 280ns

The frequency of Spread Spectrum is 33KHz.

Note: Bits 0:5 only for Winbond internal and BOIS program use; the release version please reserved these bits

7.13 Register 12: SKEW Control (Default = 84h)

BIT

7

NAME

PWD

DESCRIPTION

CPU_PCI_SKEW [2]

CPU_PCI_SKEW [1]

CPU_PCI_SKEW [0]

1

0

CPU to PCI skew control, Skew resolution is 300ps

The decision of skew direction is same as CPU_PCI_SKEW

[2:0] setting.

6

5

4

3

Reserved

0

Reserved

FIX_HTTCLK_PCI

0: normal mode: the HTTCLK/PCI is synchronous with CPU

1: fix mode: the HTTCLK/PCI is asynchronous with CPU

and fix in 72/36 MHz output frequency.

2

1

0

CPU_HTTCLK_SKEW [2]

CPU_HTTCLK_SKEW [1]

CPU_HTTCLK_SKEW [0]

1

0

CPU to PCI_HTTCLK skews control. Skew resolution is

300ps

The decision of skew direction is same as

CPU_HTTCLK_SKEW [2:0] setting.

Note: The skew rate control select bit fit value Please felloe below table.

SKEW bit[2:0]

000

-4

001

-3

010

-2

011

-1

100

0

101

1

110

2

111

3

Unit

Note: Each unit means 300ps

Note: skew bits only for Winbond internal and BOIS program use; the release version please reserved these bits.

- 14 -

W83194BR-K8/W83194BG-K8

CLOCK GEN. FOR AMD^®K8™ MICROPROCESSORS AND CHIPSET

7.14 Register 13: Winbond Chip ID (Default = 46h) (Read Only)

BIT

7

NAME

PWD

DESCRIPTION

Winbond Chip ID. W83194BR-K8 (SA5846).

Winbond Chip ID.

CHPI_ID [7]

CHPI_ID [6]

CHPI_ID [5]

CHPI_ID [4]

CHPI_ID [3]

CHPI_ID [2]

CHPI_ID [1]

CHPI_ID [0]

0

1

0

1

0

6

5

Winbond Chip ID.

4

Winbond Chip ID.

3

Winbond Chip ID.

2

Winbond Chip ID.

1

Winbond Chip ID.

0

Winbond Chip ID.

7.15 Register 14: Winbond Chip ID (Default = 55h) (Read Only)

BIT

7

NAME

PWD

DESCRIPTION

MAS_ID [1]

0

1

0

1

0

1

0

1

Winbond Master-Chip ID.

Winbond Sub-Chip ID.

6

MAS_ID [0]

5

SUB_ID [1]

4

SUB_ID [0]

3

MAS_VER_ID [1]

MAS_VER_ID [0]

SUB_VER_ID [1]

SUB_VER_ID [0]

Winbond Master’s Version ID.

Winbond Sub’s Version ID.

2

1

0

Note: The slew rate control select bit fit value Please felloe below table.

S2

0

S1

0

SLEW RATE STATUS

Weak

0

1

Normal

1

0

Strong

1

More Strong

Publication Release Date: May 2006

Revision 0.61

- 15 -

W83194BR-K8/W83194BG-K8

CLOCK GEN. FOR AMD^®K8™ MICROPROCESSORS AND CHIPSET

7.16 Register 15: REF & PCI Output Slew-Rate control (Default = 25h)

BIT

7

NAME

PWD

DESCRIPTION

REF Pin 1, 48, 45 output slew rate control bit.

This slew rate status default is Weak

REF_S1

REF_S2

PCIA_S1

PCIA_S2

PCIB_S1

PCIB_S2

PCIF_S1

PCIF_S2

0

1

0

1

0

1

6

5

PCI Pin 12, 13,14,21,22 output slew rate control bit.

This slew rate status default is normal

PCI Pin 17, 18, 24 output slew rate control bit.

This slew rate status default is strong

4

3

2

1

PCI Pin 23 output slew rate control bit.

This slew rate status default is strong

0

7.17 Register 16: HTTCLK & 24_48MHz Slew-Rate control (Default = 95h)

BIT

7

NAME

HTTCLK_0_S1

HTTCLK_0_S2

HTTCLK_12_S1

HTTCLK_12_S2

HTTCLK_3_S1

HTTCLK_3_S2

P24M_S1

PWD

DESCRIPTION

HTTCLK_0 Pin 6 output slew rate control bit.

This slew rate status default is normal

HTTCLK_1:2 Pin 7, 8 output slew rate control bit.

This slew rate status default is strong

1

0

1

0

1

0

1

6

5

4

3

HTTCLK_3 Pin 11 output slew rate control bit.

This slew rate status default is strong

2

1

24_48MHz Pin 28 output slew rate control bit.

This slew rate status default is strong

0

P24M_S2

7.18 Register 17: Slew Rate Control (Default = AAh)

BIT

7

NAME

P48M_S1

PWD

DESCRIPTION

48MHz Pin 31 output slew rate control bit.

This slew rate status default is Normal

1

0

1

0

1

X

6

P48M_S2

CPU_S1

CPU_S2

IVAL<3>

IVAL<2>

IVAL<1>

IVAL<0>

5

CPU Pin 36,37,40,41 output slew rate control bit.

This slew rate status default is Normal

Charge pump current selection

4

3

2

Charge pump current selection

1

Charge pump current selection

0

Charge pump current selection

Note: This Byte 0:3 only for Winbond internal and BIOS program use; the release version please reserved this byte.

- 16 -

W83194BR-K8/W83194BG-K8

CLOCK GEN. FOR AMD^®K8™ MICROPROCESSORS AND CHIPSET

8. ACCESS INTERFACE

The W83194BR-K8 supports I²C Serial Bus Block Read/Block Write and Byte-Data Read/Write

protocol for microprocessor to read/write internal registers The I²C address is 0xD2h.

The register number is incremented by one if using byte data read/write protocol.

Example: In block mode, byte number of program register is 1

In byte mode, byte number of program register is 2 (Byte number of block mode +1)

Block Read and Block Write Protocol

8.1 Block Write protocol

8.2 Block Read protocol

## In block mode, the command code must filled 00H

8.3 Byte Write protocol

8.4 Byte Read protocol

Publication Release Date: May 2006

- 17 -

Revision 0.61

W83194BR-K8/W83194BG-K8

CLOCK GEN. FOR AMD^®K8™ MICROPROCESSORS AND CHIPSET

9. SPECIFICATIONS

9.1 ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed in this table may cause permanent damage to the device.

Precautions should be taken to avoid application of any voltage higher than the maximum rated

voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability.

Unused inputs must always be tied to an appropriate logic voltage level (Ground or VDD) by external

of internal pull-up or pull-down resistors.

PARAMETER

Absolute 3.3V Core Supply Voltage

Absolute 3.3V I/O Supple Voltage

Operating 3.3V Core Supply Voltage

Operating 3.3V I/O Supple Voltage

Storage Temperature

RATING

-0.5V to +4.6V

- 0.5 V to + 4.6 V

3.135V to 3.465V

- 65°C to + 150°C

- 55°C to + 125°C

0°C to + 70°C

2000V

Ambient Temperature

Operating Temperature

Input ESD protection (Human body model)

9.2 DC Operating Characteristics

VDDREF =VDDA=VDDCPU=VDDPCI=VDD48= 3.3V ± 5 %, TA = 0°C to +70°C, Cl=10pF

PARAMETER

Input Low Voltage

SYMBOL

V_IL

MIN

2.0

2.4

MAX UNITS

TEST CONDITIONS

0.8

0.4

V_dc

mA

Input High Voltage

Output Low Voltage

Output High Voltage

Operating Supply Current

V_IH

V_OL

All outputs using 3.3V power

CPU = 100 to 309 MHz

V_OH

I_dd

300

PCI = 33.3 MHz with load

Input pin capacitance

Output pin capacitance

Input pin inductance

Cin

Cout

Lin

5

6

7

pF

nH

- 18 -

W83194BR-K8/W83194BG-K8

CLOCK GEN. FOR AMD^®K8™ MICROPROCESSORS AND CHIPSET

9.3 Clock Skews

VDDREF =VDDA=VDDCPU=VDDPCI=VDD48= 3.3V ± 5 %, TA = 0°C to +70°C, Cl=10pF

PARAMETER

MIN

TYP

MAX

UNITS

TEST CONDITIONS

CPU to CPU Skew

250

ps

Crossing point for CPUT rising

edge

CPU to PCI Skew

500

1000

500

ps

Ps

ps

Crossing point for CPUT rising

edge and 1.5V for PCI clocks

CPU to HTTCLK Skew

PCI to PCI Skew

Crossing point for CPUT rising

edge and 1.5V for HTTCLK clocks

Measured between rising edges

at 1.5V

PCI to HTTCLK Skew

HTTCLK to HTTCLK Skew

48MHz to 48MHz Skew

REF to REF Skew

Measured between rising edges

at 1.5V

Measured between rising edges

at 1.5V

Measured between rising edges

at 1.5V

Measured between rising edges

at 1.5V

Publication Release Date: May 2006

Revision 0.61

- 19 -

W83194BR-K8/W83194BG-K8

CLOCK GEN. FOR AMD^®K8™ MICROPROCESSORS AND CHIPSET

9.4 CPU Clock Electrical Characteristics

VDDCPU= 3.3V ± 5 %, TA = 0°C to +70°C, Cl=10pF,

PARAMETER

Rise Edge Rate

MIN

TYP

MAX UNITS

TEST CONDITIONS

2

10

V/ns

V

Measured at CPU test load. 0V ±

400mV (differential measurement)

Fall Edge Rate

2

10

Measured at CPU test load. 0V ±

400mV (differential measurement)

V_DIFF: Differential Voltage

(Single ended)

0.4

1.25

2.3

Measured at CPU test load. (Single

ended measurement)

-150

+150

1.45

+200

53

mV

V

Measured at CPU test load. (Single

ended measurement)

Δ V_DIFF

V_{DIFF_DC}Magnitude

V_CMCommon Mode 1.05

:

Change in

:

Measured at CPU test load. (Single

ended measurement)

Voltage

-200

45

mV

%

Measured at CPU test load. (Single

ended measurement)

ΔV_CM: Change Common

Voltage

Duty Cycle

50

Measure at the differential crossing

point

Cycle to Cycle Jitter

100

200

ps

Measured at the differential crossing

point. Maximum difference of cycle

time between two adjacent cycles.

Frequency Stabilization

from Power-up (cold

start)

0

3

ms

Measured from full supply voltage

Single-Ended Measurement Definitions

V_DIFF

V_DIFF=V_{DIFF_0}-V_{DIFF_1}

V_DIFF

V_{DIFF_0}

V_{DIFF_1}

V_CM=V_{CM_0}-V_{CM_1}

V_CM

V_{CM_0}

V_{CM_1}

V_CM

- 20 -

W83194BR-K8/W83194BG-K8

CLOCK GEN. FOR AMD^®K8™ MICROPROCESSORS AND CHIPSET

9.5 HTTCLK Clock Electrical Characteristics

VDDPCI= 3.3V ± 5 %, TA = 0°C to +70°C, Test load, Cl=10pF,

PARAMETER

Rise Edge Rate

MIN

1

MAX

4

UNITS

V/ns

ps

TEST CONDITIONS

Measured from 20% to 60%

Fall Edge Rate

1

4

Cycle to Cycle jitter

250

Measured on rising edge at 1.5V,

Maximum difference of cycle time

between two adjacent cycles.

Jitter Accumulated

Duty Cycle

-1000

45

1000

55

ps

%

Measured using the JIT2 software

package

Measured on rising and falling edge at

1.5V

Pull-Up Current Min

Pull-Up Current Max

Pull-Down Current Min

Pull-Down Current Max

-33

mA

Vout=1.0V

Vout=3.135V

Vout=1.95V

Vout=0.4V

-33

38

30

9.6 PCI Clock Electrical Characteristics

VDDPCI= 3.3V ± 5 %, TA = 0°C to +70°C, Test load, Cl=10pF,

PARAMETER

Rise Edge Rate

MIN

1

MAX

4

UNITS

V/ns

ps

TEST CONDITIONS

Measured from 20% to 60%

Fall Edge Rate

1

4

Cycle to Cycle jitter

250

Measured on rising edge at 1.5V,

Maximum difference of cycle time

between two adjacent cycles.

Jitter Accumulated

Duty Cycle

-1000

45

1000

55

ps

%

Measured using the JIT2 software

package

Measured on rising and falling edge at

1.5V

Pull-Up Current Min

Pull-Up Current Max

Pull-Down Current Min

Pull-Down Current Max

-33

mA

Vout=1.0V

Vout=3.135V

Vout=1.95V

Vout=0.4V

-33

38

30

Publication Release Date: May 2006

Revision 0.61

- 21 -

W83194BR-K8/W83194BG-K8

CLOCK GEN. FOR AMD^®K8™ MICROPROCESSORS AND CHIPSET

9.7 24M, 48M Clock Electrical Characteristics

VDD48= 3.3V ± 5 %, TA = 0°C to +70°C, Test load, Cl=10pF,

PARAMETER

Rise Edge Rate

MIN

0.5

MAX

2

UNITS

V/ns

ps

TEST CONDITIONS

Measured from 20% to 80%

Fall Edge Rate

2

Cycle to Cycle jitter

500

Measured on rising edge at 1.5V,

Maximum difference of cycle time

between two adjacent cycles.

Jitter Accumulated

Duty Cycle

-1000

45

1000

55

ps

%

Measured using the JIT2 software

package

Measured on rising and falling edge at

1.5V

Pull-Up Current Min

Pull-Up Current Max

Pull-Down Current Min

Pull-Down Current Max

-29

mA

Vout=1.0V

Vout=3.135V

Vout=1.95V

Vout=0.4V

-23

27

29

9.8 REF Electrical Characteristics

VDDREF= 3.3V ± 5 %, TA = 0°C to +70°C, Test load, Cl=10pF,

PARAMETER

Rise Edge Rate

MIN

0.5

MAX

2

UNITS

V/ns

ps

TEST CONDITIONS

Measured from 20% to 80%

Fall Edge Rate

2

Cycle to Cycle jitter

1000

Measured on rising edge at 1.5V,

Maximum difference of cycle time

between two adjacent cycles.

Jitter Accumulated

Duty Cycle

-1000

45

1000

55

ps

%

Measured using the JIT2 software

package

Measured on rising and falling edge at

1.5V

Pull-Up Current Min

Pull-Up Current Max

Pull-Down Current Min

Pull-Down Current Max

-33

mA

Vout=1.0V

Vout=3.135V

Vout=1.95V

Vout=0.4V

-33

38

30

- 22 -

W83194BR-K8/W83194BG-K8

CLOCK GEN. FOR AMD^®K8™ MICROPROCESSORS AND CHIPSET

10. ORDERING INFORMATION

PART NUMBER

W83194BR-K8

W83194BG-K8

PACKAGE TYPE

48 PIN SSOP

48 PIN SSOP(Lead free part)

PRODUCTION FLOW

Commercial, 0°C to +70°C

11. HOW TO READ THE TOP MARKING

W83194BR-K8

28051234

520GB

A

SA

W83194BG-K8

28051234

520GB

A

SA

1st line: Winbond logo and the type number: Normal: W83194BR-K8, Lead free part: W83194BG-K8

2nd line: Tracking code 2 8051234

2: wafers manufactured in Winbond FAB 2

8051234: wafer production series lot number

3rd line: Tracking code 520 G B A SA

520: packages made in '2005, week 20

G: assembly house ID; O means OSE, G means GR

B: Internal use code

A: IC revision

SA: Internal use code

Publication Release Date: May 2006

- 23 -

Revision 0.61

W83194BR-K8/W83194BG-K8

CLOCK GEN. FOR AMD^®K8™ MICROPROCESSORS AND CHIPSET

12. PACKAGE DRAWING AND DIMENSIONS

- 24 -

W83194BR-K8/W83194BG-K8

CLOCK GEN. FOR AMD^®K8™ MICROPROCESSORS AND CHIPSET

Important Notice

Winbond products are not designed, intended, authorized or warranted for use as components

in systems or equipment intended for surgical implantation, atomic energy control

instruments, airplane or spaceship instruments, transportation instruments, traffic signal

instruments, combustion control instruments, or for other applications intended to support or

sustain life. Further more, Winbond products are not intended for applications wherein failure

of Winbond products could result or lead to a situation wherein personal injury, death or

severe property or environmental damage could occur.

Winbond customers using or selling these products for use in such applications do so at their

own risk and agree to fully indemnify Winbond for any damages resulting from such improper

use or sales.

Publication Release Date: May 2006

- 25 -

Revision 0.61

型号:	W83194BG-B
生命周期：	Obsolete
包装说明：	,
Reach Compliance Code：	compliant
风险等级：	5.83
Base Number Matches：	1

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