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产品型号W83321G的概述

W83321G芯片的概述 W83321G是一款由Winbond Electronics Corporation(胜利电子)设计和制造的高度集成的系统监控芯片,主要用于计算机主板和其他电子设备的健康监测和管理。这款芯片在各类嵌入式系统中得到了广泛应用,尤其在服务器和个人计算机中表现尤为出色。W83321G以其高效能和低功耗的特性为开发者提供了一种理想的解决方案,以保证系统的稳定性与安全性。 该芯片不仅能实时监控系统的多个关键参数,比如温度、电压和风扇转速,还支持故障侦测和报警功能。这为系统管理员提供了充分的信息,以便及时采取相应的预防措施,减少硬件故障带来的潜在损失。 W83321G的详细参数 W83321G芯片的主要技术参数如下: - 电源电压:2.7V 至 5.5V - 工作温度范围:-40°C 至 +85°C - 输入电压监控范围:0V 至 5V(支持多个电源监控) - 温度监控范...

产品型号W83321G的Datasheet PDF文件预览

W83321S/W83321G  
Winbond  
N-Channel FET Synchronous Buck  
Regulator Controller  
W83321S  
W83321G  
Publication Release Date: January, 2006  
- 1 -  
Revision 0.51  
W83321S/W83321G  
W83321S  
Data Sheet Revision History  
VERSION  
PAGES  
DATES  
VERSION  
MAIN CONTENTS  
ON WEB  
2004/3/19  
0.5  
N.A  
All versions before 0.5 are for internal use only.  
1. Add Pb-free part no:W83321G  
1
2
5
2005/1/21  
0.51  
N.A  
2. Add separate VCC12 rail for VBOOT  
application circuit.  
Please note that all data and specifications are subject to change without notice. All the trademarks of  
products and companies mentioned in this datasheet belong to their respective owners.  
LIFE SUPPORT APPLICATIONS  
These products are not designed for use in life support appliances, devices, or systems where  
malfunction of these products can reasonably be expected to result in personal injury. Winbond  
customers using or selling these products for use in such applications do so at their own risk and  
agree to fully indemnify Winbond for any damages resulting from such improper use or sales.  
- 2 -  
W83321S/W83321G  
Table of Content-  
1.  
GENERAL DESCRIPTION ......................................................................................................... 4  
FEATURES................................................................................................................................. 4  
APPLICATIONS.......................................................................................................................... 5  
PIN-OUT ..................................................................................................................................... 5  
PIN DESCRIPTION..................................................................................................................... 6  
INTERNAL BLOCK DIAGRAM ................................................................................................... 7  
APPLICATION CIRCUIT............................................................................................................. 8  
LAYOUT PLACEMENT............................................................................................................... 9  
ELECTRICAL CHARACTERISTICS......................................................................................... 10  
TYPICAL OPERATING WAVEFORMS .................................................................................... 11  
PACKAGE DIMENSION OUTLINE........................................................................................... 16  
ORDERING INSTRUCTION..................................................................................................... 17  
HOW TO READ THE TOP MARKING...................................................................................... 17  
2.  
3.  
4.  
5.  
6.  
7.  
8.  
9.  
10.  
11.  
12.  
13.  
Publication Release Date: January, 2006  
- 3 -  
Revision 0.51  
W83321S/W83321G  
1. GENERAL DESCRIPTION  
The W83321S is a high-speed, N-Channel synchronous buck regulator controller. The W83321S  
employs fixed-frequency voltage-mode PWM control architecture. Both high-side and low-side  
MOSFETs are lower cost N-Channel type. The regulator is biased from a 5V rail and the power for the  
high-side MOSFET can be supplied by a separate 12V rail or supplied from a local charge pump.  
Current limit is achieved by monitoring the voltage drop across the on resistance of the low-side  
MOSFET. This method eliminates the requirement of extra current sensing resistor and avoids false  
trigger of OC protection when VIN varies. The adaptive non-overlapping MOSFET gate drivers help  
avoid potential shoot-through problems while maintaining high efficiency.  
2. FEATURES  
y
y
Operates from +5V Input  
0.8V to VIN Output Range  
- 0.8V Internal Reference  
- ±1.5% Over Line Voltage and Temperature  
Drives N-Channel MOSFETs  
Simple Single-Loop Control Design  
- Voltage-Mode PWM Control  
Fast Transient Response  
y
y
y
y
Lossless, Programmable Overcurrent Protection  
- Uses Lower MOSFET’s Rds (on)  
- Current limit without sense resistor  
Small Converter Size  
y
- 250 kHz Fixed Frequency Oscillator  
- Internal Soft Start  
- Tiny plastic SOP-8 package  
- 4 -  
 
W83321S/W83321G  
3. APPLICATIONS  
y
y
Motherboard Power Supplies Regulation  
Subsystem Power Supplies  
- PCI/AGP/GTL+ Buses  
- ACPI Power Control  
- SSTL-2 and DDR SDRAM Bus Termination Supply  
Cable Modems, Set Top Boxes, and DSL Modems  
DSP and Core Communications Processor Supplies  
Memory Power Supplies  
y
y
y
y
y
y
y
Personal Computer Peripherals  
Industrial Power Supplies  
5V-Input DC-DC Regulators  
Low-Voltage Distributed Power Supplies  
4. PIN-OUT  
1
2
3
4
8
7
6
5
ISEN  
COMP  
FB  
BOOT  
UGATE  
GND  
W83321  
VCC  
LGATE  
Publication Release Date: January, 2006  
Revision 0.51  
- 5 -  
 
W83321S/W83321G  
5. PIN DESCRIPTION  
PIN  
NAME  
FUNCTION  
Supply rail for the high-side MOSFET driver. A bootstrap circuit may be used to  
create a BOOT voltage or a separate 12V supply can be used.  
1
BOOT  
Gate drive for the high-side N-channel MOSFET. This pin is also monitored by  
the adaptive shoot through protection circuitry to determine when the high-side  
MOSFET has turned off.  
2
3
4
UGATE  
GND  
Ground for analog circuit. Connect it to system ground.  
Gate drive for the low-side N-channel MOSFET. This pin is also monitored by  
the adaptive shoot through protection circuitry to determine when the low-side  
MOSFET has turned off.  
LGATE  
5
6
VCC  
FB  
+5V supply rail for the lower gate driver and control logic circuit.  
Inverting Input of the Error Amplifier. This pin is available for compensation of  
the control loop.  
Internal Error Amplifier Output Pin. This pin is available for compensation of the  
7
8
COMP  
ISEN  
control loop and pulling this pin low with an open drain device will shutdown the  
IC.  
Current limit threshold setting. Connect a resistor (ROCSET) between this pin and  
the drain of the low-side MOSFET.  
- 6 -  
 
W83321S/W83321G  
6. INTERNAL BLOCK DIAGRAM  
VDD  
POR  
90µA  
ISEN  
Soft Start  
VREF  
0.8V  
Ramp  
Control  
Logic  
BOOT  
+
Output  
Clamp  
UGATE  
EA  
-
Gate  
Control  
Logic  
FB  
+
-
COMP  
VDD  
Oscillator  
250KHz  
Ramp  
Generator  
LGATE  
1.5Vp-p  
GND  
MOSFET Gate Drivers  
Power for the high-side driver is through the BOOT pin. This voltage can be supplied by a separate,  
higher voltage source, or supplied from a local charge pump structure or even the combination of the  
two.  
Since the voltage of the low-side MOSFET gate and the high-side MOSFET gate are being monitored  
to determine the state of the MOSFET, it should be considered carefully to add external components  
between the gate drivers and their respective MOSFET gates. Doing so may interfere with the shoot-  
through protection.  
Current Limit (Over current protection)  
Current limit is realized by sensing the voltage across the low-side MOSFET while it is on. This  
method enhances the converter's effeciency and reduces cost by eliminating a current sensing  
resistor.  
While low-side MOSFET is turned on, a constant current of 90uA is forced through ROCSET which is an  
external resistor connected between phase and ISEN, causing a fixed voltage drop. This fixed voltage  
is compared against VDS and if the latter is higher, the chip enters current limit mode. In the current  
limit mode both the high-side and low-side MOSFETS are turned off. After a 25ms delay, a soft-start  
Publication Release Date: January, 2006  
- 7 -  
Revision 0.51  
 
W83321S/W83321G  
cycle is initiated. If the cause of the overcurrent is still present after the delay interval, the current limit  
would be triggered again. The shut dowm - delay - soft start cycle will be repeated indefinitely untill the  
overcurrent event has cleared.  
IPEAK = (IOCSET x ROCSET) / RDS(ON) RDS(ON):Low Side MOSFET Resistance  
7. APPLICATION CIRCUIT  
Local charge pump for VBOOT application:  
R1 3.7K  
C1 0.1uF  
VCC5  
U1  
D1  
1
2
3
4
8
7
6
5
BOOT  
UGATE  
GND  
ISEN  
COMP  
FB  
C4 (OPT)  
C2  
2000uF 1uF  
N DSG  
C3 Q1  
1N4148/Shuttky  
3
3
VOUT=0.8X(R5+R6)/R6  
L1 3.3uH  
C5 2.2nF  
R2 100K  
VCC5  
C6  
2000uF  
C7  
2000uF  
C8  
0.1uF  
R3  
2.2  
Q2  
R4 10  
LGATE  
VCC  
N DSG  
W83321S  
C9  
1uF  
C10  
6.8nF  
R5 16K(1%)  
R6  
7.5K(1%)  
Separate VCC12 rail for VBOOT application:  
R1 3.7K  
R7 10  
VCC12  
VCC5  
C1  
1000uF  
C11  
1uF  
U1  
1
2
3
4
8
BOOT  
ISEN  
C4 (OPT)  
C2  
C3 Q1  
2000uF 1uF  
N DSG  
3
7
UGATE  
GND  
COMP  
VOUT=0.8X(R5+R6)/R6  
L1 3.3uH  
6
C5 2.2nF  
R4 10  
R2 100K  
VCC5  
FB  
C6  
2000uF  
C7  
2000uF  
C8  
0.1uF  
R3  
2.2  
Q2  
N DSG  
3
5
LGATE  
VCC  
W83321S  
C9  
1uF  
C10  
6.8nF  
R5 16K(1%)  
R6  
7.5K(1%)  
- 8 -  
 
W83321S/W83321G  
8. LAYOUT PLACEMENT  
G
S
D
C3  
1uF  
C2  
2000uF  
Q1  
G
S
L1  
VCC  
D
C9  
1uF  
Q2  
W83321S  
C6  
2000uF  
C7  
2000uF  
BOOT  
PIN1  
C1 0.1uF  
Layout Notes:  
1.Put Q1 and Q2 as close as possible and using wide,short  
printed circuit traces between Q1 source and Q2 drain.  
2.Put C2 and C3 to be near the Q1 drain and Q2 source nodes.  
3.Put C1 as close as to BOOT pin.  
4.Put C9 as close as to VCC pin.  
Publication Release Date: January, 2006  
- 9 -  
Revision 0.51  
 
W83321S/W83321G  
9. ELECTRICAL CHARACTERISTICS  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP MAX UNITS  
VCC SUPPLY CURRENT  
Nominal Supply  
EN=VCC; UGATE and LGATE  
Open  
ICC  
-
3
-
mA  
POWER-ON RESET  
Rising VDD  
Threshold  
-
-
4.3  
3.7  
4.5  
-
V
V
Falling VDD  
Threshold  
OSCILLATOR  
Free Running  
Frequency  
200  
-
250  
1.5  
300  
-
kHz  
VP-P  
Ramp Amplitude  
ΔVOSC  
REFERENCE  
Reference Voltage  
Tolerance  
VREF  
-1.5  
-
-
1.5  
-
%
V
Reference Voltage  
ERROR AMPLIFIER  
DC Gain  
0.8  
-
-
-
85  
5.5  
4.1  
-
-
-
dB  
Gain-Bandwidth  
Slew Rate  
MHz  
V/µS  
GATE DRIVERS  
High-side Gate  
Source  
IHGATE-SRC  
IHGATE-SNK  
ILGATE-SRC  
ILGATE-SNK  
VBOOT=12V,VUGATE=6V  
VBOOT=12V,VUGATE=6V  
VCC=5V, VLGATE=2.5V  
VCC=5V, VLGATE=2.5V  
250  
600  
250  
300  
-
-
-
-
-
-
-
-
mA  
mA  
mA  
mA  
High-side Gate Sink  
Low-side Gate  
Source  
Low-side Gate Sink  
PROTECTION/DISABLE  
ISEN Current  
Source  
ISEN  
72  
-
90  
108  
-
µA  
V
Disable Threshold  
VCOMP  
0.4  
- 10 -  
 
W83321S/W83321G  
10. TYPICAL OPERATING WAVEFORMS  
Dead Time: VCC=5V; VOUT=2.5V  
Channel 1: UGATE Channel 2: LGATE  
Dead Time: VCC=5V; VOUT=2.5V  
Channel 1: UGATE Channel 2: LGATE  
Publication Release Date: January, 2006  
Revision 0.51  
- 11 -  
 
W83321S/W83321G  
Power On: VCC=5V; VOUT=2.5V  
Channel 1: VCC Channel 2: VOUT  
Power Off: VCC=5V; VOUT=2.5V  
Channel 1: VCC Channel 2: VOUT  
- 12 -  
W83321S/W83321G  
Bootstrap: VCC=5V; VOUT=2.5V  
Channel 1: UGATE Channel 2: LGATE Channel 3: BOOT  
Soft Start: VCC=5V; VOUT=2.5V  
Channel 1: UGATE Channel 2: VOUT  
Publication Release Date: January, 2006  
Revision 0.51  
- 13 -  
W83321S/W83321G  
Load Transient: VCC=5V; VOUT=2.5V; Cout=2200uF  
Channel 3: VOUT Channel 4: Iout (Loading=0Æ5A)  
Load Transient: VCC=5V; VOUT=2.5V; Cout=2200uF  
Channel 3: VOUT Channel 4: Iout (Loading=5Æ0A)  
- 14 -  
W83321S/W83321G  
Short Hiccup: VCC=5V; VOUT=2.5V; Cout=2200uF with R=0.1(ohm) load.  
Channel 1: UGATE Channel 2: VOUT Channel4: Iout  
Publication Release Date: January, 2006  
Revision 0.51  
- 15 -  
W83321S/W83321G  
11. PACKAGE DIMENSION OUTLINE  
8L SOP (150mil)  
- 16 -  
 
W83321S/W83321G  
12. ORDERING INSTRUCTION  
PART NO.  
PACKAGE  
REMARKS  
W83321S  
8-pin SOP  
Operation - Commercial 0~70  
Operation - Commercial 0~70℃  
W83321G  
8-pin SOP  
Pb-free package  
13. HOW TO READ THE TOP MARKING  
W83  
321S  
323GA  
W83  
321G  
323GA  
Left Line: Winbond Logo  
1st and 2nd Line: the part number,321G is for Pb-free package  
3rd Line: Tracking Code  
323: packages assembled in Year 03’, week 23  
G: assembly house ID; G means GR, O means OSE, etc.  
A: the IC version  
Publication Release Date: January, 2006  
Revision 0.51  
- 17 -  
 
W83321S/W83321G  
Please note that all data and specifications are subject to change without notice. All the trade  
marks of products and companies mentioned in this data sheet belong to their respective  
owners.  
Important Notice  
Winbond products are not designed, intended, authorized or warranted for use as components  
in systems or equipment intended for surgical implantation, atomic energy control  
instruments, airplane or spaceship instruments, transportation instruments, traffic signal  
instruments, combustion control instruments, or for other applications intended to support or  
sustain life. Further more, Winbond products are not intended for applications wherein failure  
of Winbond products could result or lead to a situation wherein personal injury, death or  
severe property or environmental damage could occur.  
Winbond customers using or selling these products for use in such applications do so at their  
own risk and agree to fully indemnify Winbond for any damages resulting from such improper  
use or sales.  
- 18 -  
配单直通车
W83321G产品参数
型号:W83321G
是否Rohs认证: 符合
生命周期:Obsolete
零件包装代码:SOIC
包装说明:HSOP, SOP8,.25
针数:8
Reach Compliance Code:unknown
ECCN代码:EAR99
HTS代码:8542.39.00.01
风险等级:5.81
模拟集成电路 - 其他类型:SWITCHING CONTROLLER
控制模式:VOLTAGE-MODE
控制技术:PULSE WIDTH MODULATION
标称输入电压:5 V
JESD-30 代码:R-PDSO-G8
长度:4.85 mm
湿度敏感等级:3
功能数量:1
端子数量:8
最高工作温度:70 °C
最低工作温度:
封装主体材料:PLASTIC/EPOXY
封装代码:HSOP
封装等效代码:SOP8,.25
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, HEAT SINK/SLUG
峰值回流温度(摄氏度):260
认证状态:Not Qualified
座面最大高度:1.73 mm
子类别:Switching Regulator or Controllers
表面贴装:YES
切换器配置:PUSH-PULL
最大切换频率:300 kHz
温度等级:COMMERCIAL
端子形式:GULL WING
端子节距:1.27 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:40
宽度:3.9 mm
Base Number Matches:1
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